2.1.1. Programmed Input/Output Design Example Functional Description

F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

Download PDF

ID 683372

Date 1/29/2024

Version

Public

A newer version of this document is available. Customers should click here to go to the newest version.

Visible to Intel only — GUID: evh1630621350139

Ixiasoft

View Details

Document Table of Contents

Document Table of Contents x

1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

2. Design Example Description x

2.1. Programmed Input/Output Design Example 2.2. Single Root I/O Virtualization (SR-IOV) Design Example 2.3. Performance Design Example

2.1. Programmed Input/Output Design Example x

2.1.1. Programmed Input/Output Design Example Functional Description 2.1.2. Programmed Input/Output Design Example Limitation 2.1.3. Programmed Input/Output Design Example Simulation Testbench

2.1.1. Programmed Input/Output Design Example Functional Description x

2.1.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.1.1.2. PIO Application (APPS) 2.1.1.3. On-Chip Memory (MEM) 2.1.1.4. F-Tile Reference and System PLL Clocks IP 2.1.1.5. Reset Release IP

2.1.1.2. PIO Application (APPS) x

2.1.1.2.1. Scheduler 2.1.1.2.2. Read Write Module 2.1.1.2.3. Avalon-MM Interface 2.1.1.2.4. Completion Module 2.1.1.2.5. Width Adapter

2.2. Single Root I/O Virtualization (SR-IOV) Design Example x

2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description 2.2.2. SR-IOV Design Example Limitation 2.2.3. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench

2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description x

2.2.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.1.2. SR-IOV Applications (APPS)

2.2.1.2. SR-IOV Applications (APPS) x

2.2.1.2.1. Access Parser 2.2.1.2.2. Access Router 2.2.1.2.3. Completion 2.2.1.2.4. PF Segram 2.2.1.2.5. VF Segram 2.2.1.2.6. F-Tile Reference and System PLL Clocks IP 2.2.1.2.7. Reset Release IP

2.3. Performance Design Example x

2.3.1. Performance Design Example Functional Description 2.3.2. Performance Design Example Simulation Testbench

3. Quick Start Guide x

3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Hardware and Software Requirements 3.6. Installing the Linux Kernel Driver 3.7. Running the Design Example

3.3. Simulating the Design Example x

3.3.1. Steps to Run Simulation 3.3.2. Testbench

3.3.1. Steps to Run Simulation x

3.3.1.1. Steps to Run Simulation : VCS* 3.3.1.2. Steps to Run Simulation : VCS* MX 3.3.1.3. Steps to Run Simulation : QuestaSim* / ModelSim* - Intel® FPGA Starter Edition / Questa* Intel® FPGA Starter Edition 3.3.1.4. Steps to Run Simulation : Xcelium* 3.3.1.5. Steps to Run Simulation : Riviera-PRO*

3.3.2. Testbench x

3.3.2.1. Test Driver Module 3.3.2.2. PIO Design Example Testbench 3.3.2.3. SR-IOV Design Example Testbench 3.3.2.4. Performance Design Example Testbench

3.7. Running the Design Example x

3.7.1. Running the PIO Design Example 3.7.2. Running the SR-IOV Design Example 3.7.3. Running the Performance Design Example

1. Acronyms

2. Design Example Description

2.1. Programmed Input/Output Design Example

2.1.1. Programmed Input/Output Design Example Functional Description

2.1.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT)

2.1.1.2. PIO Application (APPS)

2.1.1.2.1. Scheduler

2.1.1.2.2. Read Write Module

2.1.1.2.3. Avalon-MM Interface

2.1.1.2.4. Completion Module

2.1.1.2.5. Width Adapter

2.1.1.3. On-Chip Memory (MEM)

2.1.1.4. F-Tile Reference and System PLL Clocks IP

2.1.1.5. Reset Release IP

2.1.2. Programmed Input/Output Design Example Limitation

2.1.3. Programmed Input/Output Design Example Simulation Testbench

2.2. Single Root I/O Virtualization (SR-IOV) Design Example

2.2.1. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description

2.2.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT)

2.2.1.2. SR-IOV Applications (APPS)

2.2.1.2.1. Access Parser

2.2.1.2.2. Access Router

2.2.1.2.3. Completion

2.2.1.2.4. PF Segram

2.2.1.2.5. VF Segram

2.2.1.2.6. F-Tile Reference and System PLL Clocks IP

2.2.1.2.7. Reset Release IP

2.2.2. SR-IOV Design Example Limitation

2.2.3. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench

2.3. Performance Design Example

2.3.1. Performance Design Example Functional Description

2.3.2. Performance Design Example Simulation Testbench

3. Quick Start Guide

3.1. Directory Structure

3.2. Generating the Design Example

3.3. Simulating the Design Example

3.3.1. Steps to Run Simulation

3.3.1.1. Steps to Run Simulation : VCS*

3.3.1.2. Steps to Run Simulation : VCS* MX

3.3.1.3. Steps to Run Simulation : QuestaSim* / ModelSim* - Intel® FPGA Starter Edition / Questa* Intel® FPGA Starter Edition

3.3.1.4. Steps to Run Simulation : Xcelium*

3.3.1.5. Steps to Run Simulation : Riviera-PRO*

3.3.2. Testbench

3.3.2.1. Test Driver Module

3.3.2.2. PIO Design Example Testbench

3.3.2.3. SR-IOV Design Example Testbench

3.3.2.4. Performance Design Example Testbench

3.4. Compiling the Design Example

3.5. Hardware and Software Requirements

3.6. Installing the Linux Kernel Driver

3.7. Running the Design Example

3.7.1. Running the PIO Design Example

3.7.2. Running the SR-IOV Design Example

3.7.3. Running the Performance Design Example

4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives

5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

Visible to Intel only — GUID: evh1630621350139

Ixiasoft

View Details

2.1.1. Programmed Input/Output Design Example Functional Description

Figure 4. Platform Designer System Contents for F-Tile Avalon® -ST IP for PCI Express PIO Design Example [Gen4 x16 variant]The Platform Designer generates this design for up to Gen4 x16 variants.