F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 1/29/2024
Public

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2.1.1.4. F-Tile Reference and System PLL Clocks IP

This IP is required for F-Tile PCIe interface implementation to configure the reference clock for the FGT PMA and System PLL. The clock from this IP is a logical connection. It is physically inside the F-Tile Avalon Streaming Intel FPGA IP for PCI Express Hard IP. The main clock of the PIO design example originates from coreclkout_hip of the F-Tile Avalon Streaming Intel FPGA IP for PCI Express Hard IP running at 500 MHz. The clock originates from the System PLL.

The reference clock to the System PLL must adhere to the following requirements:
  • If compliance to PCIE link training timing specifications is required, the reference clock to the System PLL must be available and stable before device configuration begins. You must set the Refclk is available at power-on parameter in the System PLL IP to On. Derive the reference clock from an independent and free-running clock source. Alternately, if the reference clock from the PCIe link is guaranteed available before device configuration begins, you can use it to drive the System PLL. Once the PCIe link refclk is alive, it can never be allowed to go down.
  • If compliance to PCIE link training timing specifications is not required and the reference clock to the System PLL may not be available before device configuration begins, you must set the Refclk is available at power-on parameter in the System PLL IP to Off. In this case, you may use the reference clock from the PCIE link to drive the System PLL. The System PLL does not lock to the reference until you perform the Global Avalon memory-mapped interface write operations signaling that the reference clock is available.
    Note: Refer to the Example Flow to Indicate All System PLL Reference Clocks are Ready section in the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide to trigger the System PLL to lock to the reference clock.

Once the reference clock for the System PLL is up, it must be stable and present throughout the device operation and must not go down. If you are not able to adhere to this requirement, you must reconfigure the device.