3.1.5. Pattern Generator and Checker
|PRBS pattern generator||
The JESD204C design example PRBS pattern generator supports the following degree of polynomials:
|Ramp pattern generator||
The ramp pattern value increments by 1 for every subsequent sample with the generator width of N, and rolls over to 0 when all bits in the sample are 1.
Enable the ramp pattern generator by writing a 1 to bit 2 of the tst_ctl register of the ED control block.
|Command channel ramp pattern generator||
The JESD204C design example supports command channel ramp pattern generator per lane. The ramp pattern value increments by 1 per 6 bits of command words.
The starting seed is an increment pattern across all lanes.
|PRBS pattern checker||
The scrambling seed in the pattern checker is self-synchronized when the JESD204C IP achieves deskew alignment. The pattern checker requires 8 octets for the scrambling seed to self-synchonize.
|Ramp pattern checker||
The first valid data sample for each converter (M) is loaded as the initial value of the ramp pattern. Subsequent data samples values must increase by 1 in each clock cycle up to the maximum and then roll over to 0.
For example, when S=1, N=16 and WIDTH_MULP = 2, the data width per converter is S * WIDTH_MULP * N = 32. The maximum data sample value is 0xFFFF. The ramp pattern checker verifies that identical patterns are received across all converters.
|Command channel ramp pattern checker||
The JESD204C design example supports command channel ramp pattern checker. The first command word (6 bits) received is loaded as the initial value. Subsequent command words in the same lane must increment up to 0x3F and roll over to 0x00.
The command channel ramp pattern checker checks for ramp patterns across all lanes.
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