Visible to Intel only — Ixiasoft
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the JESD204C Design Example
4. JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
Visible to Intel only — Ixiasoft
3.1.1. JTAG to Avalon® Master Bridge
The JTAG to Avalon® Master Bridge provides a connection between the host system to access the memory-mapped JESD204C IP and the peripheral IP control and status registers through the JTAG interface.
Figure 7. System with a JTAG to Avalon® Master Bridge Core
Note: System clock must be at least 2X faster than the JTAG clock. The system clock is mgmt_clk (100MHz) in this design example.