JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683357
Date 10/21/2022
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Document Table of Contents
Document Table of Contents x
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide 2. JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the JESD204C Design Example 4. JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the JESD204C Design Example x
3.1. System Components 3.2. JESD204C Design Example Clock and Reset 3.3. JESD204C Design Example Signals 3.4. JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. SYSREF Generator 3.1.5. Pattern Generator and Checker
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the JESD204C Design Example
4. JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

3.2. JESD204C Design Example Clock and Reset

The JESD204C design example has a set of clock and reset signals.
Table 14.  Design Example Clocks
Clock Signal Direction Description
mgmt_clk Input LVDS differential clock with frequency of 100 MHz.
refclk_xcvr Input Transceiver reference clock with frequency of the PLL Selection.
refclk_core Input Core reference clock with the same frequency as refclk_xcvr.
in_sysref Input SYSREF signal.

Maximum SYSREF frequency is data rate/(66x32xE).

sysref_out Output

txlink_clk

rxlink_clk

Internal TX and RX link clock with frequency of data rate/132.

txframe_clk

rxframe_clk

Internal
  • TX and RX frame clock with frequency of data rate/33 (FCLK_MULP=4)
  • TX and RX frame clock with frequency of data rate/66 (FCLK_MULP=2)
  • TX and RX frame clock with frequency of data rate/132 (FCLK_MULP=1)

tx_fclk

rx_fclk

Internal
  • TX and RX phase clock with frequency of data rate/132, duty cycle 25% (FCLK_MULP=4)
  • TX and RX phase clock with frequency of data rate/132 (FCLK_MULP=2)
  • TX and RX phase clock is always high (1'b1) when FCLK_MULP=1
spi_SCLK Output SPI baud rate clock with frequency of 20 MHz

When you load the design example into an FPGA device, an internal ninit_done event ensures that the JTAG to Avalon Master bridge is in reset as well as all the other blocks.

The SYSREF generator has its independent reset to inject intentional asynchronous relationship for the txlink_clk and rxlink_clk clocks. This method is more comprehensive in emulating the SYSREF signal from an external clock chip.

Table 15.  Design Example Resets
Reset Signal Direction Description
global_rst_n Input Push button global reset for all blocks, except the JTAG to Avalon® Master bridge.
ninit_done Internal Output from Reset Release IP for the JTAG to Avalon® Master bridge.
mgmt_rst_in_n Internal Reset for Avalon® memory-mapped interfaces of various IPs and inputs of reset sequencers:
  • j20c_reconfig_reset for JESD204C IP duplex Native PHY
  • spi_rst_n for SPI master
  • pio_rst_n for PIO status and control
  • reset_in0 port of reset sequencer 0 and 1

The global_rst_n, hw_rst, or edctl_rst_n port asserts reset on mgmt_rst_in_n.

j20c_tx_avs_rst_n

j20c_tx_avs_rst_n

Internal Reset the JESD204C TX and RX IP Avalon® memory-mapped interfaces through the reset sequencer 0 reset_out0 port. These interfaces are reset when mgmt_rst_in_n reset is asserted.
edctl_rst_n Internal The ED Control block is reset by JTAG to Avalon® Master bridge. The hw_rst and global_rst_n ports do not reset the ED Control block.
sysref_rst_n Internal Reset for SYSREF generator block in the ED Control block using the reset sequencer 0 reset_out2 port. The reset sequencer 0 reset_out2 port deasserts the reset if the core PLL is locked.

j204c_tx_phy_rst_n

j204c_rx_phy_rst_n

Internal Reset transceiver PHY in the JESD204C IP by asserting mgmt_rst_in_n.
  • The reset sequencer 0 reset_out1 port resets j204c_tx_phy_rst_n
  • The reset sequencer 1 reset_out0 port resets j204c_rx_phy_rst_n
core_pll_rst Internal Resets the core PLL through the reset sequencer 0 reset_out0 port. The core PLL resets when mgmt_rst_in_n reset is asserted.

j204c_tx_rst_n

j204c_rx_rst_n

Internal Resets the JESD204C link and transport layers in txlink_clk, rxlink_clk, txframe_clk, and rxframe_clk domains.
  • The reset sequencer 0 reset_out5 port resets j204c_tx_rst_n. This reset deasserts if the core PLL is locked, and the tx_pma_ready and tx_ready signals are asserted.
  • The reset sequencer 1 reset_out4 port resets j204c_rx_rst_n. This reset deasserts if the core PLL is locked, and the rx_pma_ready and rx_ready signals are asserted.
hw_rst Internal Assert and deassert hw_rst by writing to the rst_ctl register of the ED Control block. mgmt_rst_in_n asserts when hw_rst is asserted.
Figure 9. Timing Diagram for the Design Example Resets
Level Two Title