50G Interlaken IP Core Release Notes

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ID 683356
Date 5/02/2016
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1. 50G Interlaken IP Core Release Notes
1. 50G Interlaken IP Core Release Notes x
1.1. 50G Interlaken IP Core v16.0 1.2. 50G Interlaken IP Core v15.1 1.3. 50G Interlaken IP Core v15.0 1.4. 50G Interlaken IP Core v14.1 1.5. 50G Interlaken IP Core v14.0 Arria 10 Edition 1.6. 50G Interlaken IP Core v14.0 1.7. 50G Interlaken IP Core v13.1 Arria 10 Edition 1.8. 50G Interlaken IP Core v13.1 1.9. 50G Interlaken IP Core v13.0
1. 50G Interlaken IP Core Release Notes

1.6. 50G Interlaken IP Core v14.0

Table 6.  Version 14.0 June 2014
Description Impact Notes
New required frequency for input clock signals tx_usr_clk and rx_usr_clk is 250 MHz, and the two clocks must be driven at the same frequency. If you provide a clock with a different frequency, it must be in the range of 200 MHz to 300 MHz, and you must modify the new hidden (RTL) parameter TX_USR_CLK_MHZ to the new value in the files <instance_name>/ilk_core_50g.sv for synthesis and <instance_name>_sim/ilk_core_50g.sv for simulation.
Upgraded to support the new IP Catalog. For more information about the IP Catalog, refer to IP Catalog and Parameter Editor in Introduction to Altera IP Cores.
Improved resource utilization by 20% and latency by 55%.
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