SDI Audio IP User Guide

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ID 683333
Date 6/15/2025
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Document Table of Contents
Document Table of Contents x
1. About the SDI Audio IP 2. SDI Audio IP Getting Started 3. SDI Audio Altera FPGA IP Functional Description 4. SDI Audio Altera FPGA IP Parameters 5. SDI Audio Altera FPGA IP Interface Signals 6. SDI Audio Altera FPGA IP Registers 7. SDI Audio IP User Guide Archives 8. Document Revision History for the SDI Audio IP User Guide
1. About the SDI Audio IP x
1.1. SDI Audio IP Device Support 1.2. SDI Audio IP Release Information 1.3. SDI Audio IP Performance and Resources
2. SDI Audio IP Getting Started x
2.1. Instantiating the SDI Audio Altera FPGA IP Simulating the Testbench
3. SDI Audio Altera FPGA IP Functional Description x
3.1. SDI Audio Embed IP 3.2. SDI Audio Extract IP 3.3. SDI Clocked Audio Input IP 3.4. SDI Clocked Audio Output IP 3.5. AES Format 3.6. Avalon Streaming Interface Audio Interface
4. SDI Audio Altera FPGA IP Parameters x
4.1. SDI Audio Embed IP Parameters 4.2. SDI Audio Extract IP Parameters 4.3. SDI Clocked Audio Input IP Parameters 4.4. SDI Clocked Audio Output IP Parameters
5. SDI Audio Altera FPGA IP Interface Signals x
5.1. SDI Audio Embed IP Signals 5.2. SDI Audio Extract IP Signals 5.3. SDI Audio Clocked Input Signals 5.4. SDI Audio Clocked Output Signals 5.5. SDI Audio IP Register Interface Signals
6. SDI Audio Altera FPGA IP Registers x
6.1. SDI Audio Embed Registers 6.2. SDI Audio Extract Registers 6.3. SDI Clocked Audio Input Registers 6.4. SDI Clocked Audio Output Registers
1. About the SDI Audio IP
2. SDI Audio IP Getting Started
3. SDI Audio Altera FPGA IP Functional Description
4. SDI Audio Altera FPGA IP Parameters
5. SDI Audio Altera FPGA IP Interface Signals
6. SDI Audio Altera FPGA IP Registers
7. SDI Audio IP User Guide Archives
8. Document Revision History for the SDI Audio IP User Guide

6.4. SDI Clocked Audio Output Registers

The following tables list the registers for the SDI Clocked Audio Output IP core.
Table 32.  SDI Clocked Audio Output Register Map
Bytes Offset Name
00h Channel 0 Register
01h Channel 1 Register
02h FIFO Status Register
03h FIFO Reset Register
Table 33.  SDI Clocked Audio Output Registers
Bit Name Access Description
Channel 0 Register
7:0 Channel 0 RW The user-defined channel number of audio channel 0.
Channel 1 Register
7:0 Channel status RAM select RW

The user-defined channel number of audio channel 1.
FIFO Status Register
7:0 Active channel RO This sticky bit reports the overflow of the clocked audio output FIFO.
FIFO Reset Register
6:0 Unused WO Reserved for future use.
7 FIFO reset WO Resets the clocked audio FIFO.
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