SDI Audio IP User Guide

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ID 683333
Date 6/15/2025
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Ixiasoft

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Document Table of Contents
Document Table of Contents x
1. About the SDI Audio IP 2. SDI Audio IP Getting Started 3. SDI Audio Altera FPGA IP Functional Description 4. SDI Audio Altera FPGA IP Parameters 5. SDI Audio Altera FPGA IP Interface Signals 6. SDI Audio Altera FPGA IP Registers 7. SDI Audio IP User Guide Archives 8. Document Revision History for the SDI Audio IP User Guide
1. About the SDI Audio IP x
1.1. SDI Audio IP Device Support 1.2. SDI Audio IP Release Information 1.3. SDI Audio IP Performance and Resources
2. SDI Audio IP Getting Started x
2.1. Instantiating the SDI Audio Altera FPGA IP Simulating the Testbench
3. SDI Audio Altera FPGA IP Functional Description x
3.1. SDI Audio Embed IP 3.2. SDI Audio Extract IP 3.3. SDI Clocked Audio Input IP 3.4. SDI Clocked Audio Output IP 3.5. AES Format 3.6. Avalon Streaming Interface Audio Interface
4. SDI Audio Altera FPGA IP Parameters x
4.1. SDI Audio Embed IP Parameters 4.2. SDI Audio Extract IP Parameters 4.3. SDI Clocked Audio Input IP Parameters 4.4. SDI Clocked Audio Output IP Parameters
5. SDI Audio Altera FPGA IP Interface Signals x
5.1. SDI Audio Embed IP Signals 5.2. SDI Audio Extract IP Signals 5.3. SDI Audio Clocked Input Signals 5.4. SDI Audio Clocked Output Signals 5.5. SDI Audio IP Register Interface Signals
6. SDI Audio Altera FPGA IP Registers x
6.1. SDI Audio Embed Registers 6.2. SDI Audio Extract Registers 6.3. SDI Clocked Audio Input Registers 6.4. SDI Clocked Audio Output Registers
1. About the SDI Audio IP
2. SDI Audio IP Getting Started
3. SDI Audio Altera FPGA IP Functional Description
4. SDI Audio Altera FPGA IP Parameters
5. SDI Audio Altera FPGA IP Interface Signals
6. SDI Audio Altera FPGA IP Registers
7. SDI Audio IP User Guide Archives
8. Document Revision History for the SDI Audio IP User Guide

1.3. SDI Audio IP Performance and Resources

The following table lists the typical resource utilization data for the SDI Audio IP with the Quartus® Prime software. Altera uses the most common configurations for each video standard and one specific variant of each device family to obtain the data.
Table 2.  SDI Audio IP Resource Utilization for Altera FPGA IP Devices
Device Audio IP ALMs Dedicated Logic Registers Block Memory Bits
Agilex™ 5 Audio Embed 986 1,144 16,384
Audio Extract 855 790 120
Clocked Audio Input 285 368 0
Clocked Audio Output 216 249 2,320
Agilex™ 7 Audio Embed 993 1,174 16,384
Audio Extract 855 790 120
Clocked Audio Input 272 368 0
Clocked Audio Output 237 253 2,320
Stratix® 10 Audio Embed 906 1256 16384
Audio Extract 840 1094 120
Clocked Audio Input 264 440 0
Clocked Audio Output 247 305 2320
Arria® 10 Audio Embed 788 1111 16384
Audio Extract 800 790 120
Clocked Audio Input 208 368 0
Clocked Audio Output 201 253 2320
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