SDI Audio IP User Guide

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ID 683333
Date 6/15/2025
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Document Table of Contents
Document Table of Contents x
1. About the SDI Audio IP 2. SDI Audio IP Getting Started 3. SDI Audio Altera FPGA IP Functional Description 4. SDI Audio Altera FPGA IP Parameters 5. SDI Audio Altera FPGA IP Interface Signals 6. SDI Audio Altera FPGA IP Registers 7. SDI Audio IP User Guide Archives 8. Document Revision History for the SDI Audio IP User Guide
1. About the SDI Audio IP x
1.1. SDI Audio IP Device Support 1.2. SDI Audio IP Release Information 1.3. SDI Audio IP Performance and Resources
2. SDI Audio IP Getting Started x
2.1. Instantiating the SDI Audio Altera FPGA IP Simulating the Testbench
3. SDI Audio Altera FPGA IP Functional Description x
3.1. SDI Audio Embed IP 3.2. SDI Audio Extract IP 3.3. SDI Clocked Audio Input IP 3.4. SDI Clocked Audio Output IP 3.5. AES Format 3.6. Avalon Streaming Interface Audio Interface
4. SDI Audio Altera FPGA IP Parameters x
4.1. SDI Audio Embed IP Parameters 4.2. SDI Audio Extract IP Parameters 4.3. SDI Clocked Audio Input IP Parameters 4.4. SDI Clocked Audio Output IP Parameters
5. SDI Audio Altera FPGA IP Interface Signals x
5.1. SDI Audio Embed IP Signals 5.2. SDI Audio Extract IP Signals 5.3. SDI Audio Clocked Input Signals 5.4. SDI Audio Clocked Output Signals 5.5. SDI Audio IP Register Interface Signals
6. SDI Audio Altera FPGA IP Registers x
6.1. SDI Audio Embed Registers 6.2. SDI Audio Extract Registers 6.3. SDI Clocked Audio Input Registers 6.4. SDI Clocked Audio Output Registers
1. About the SDI Audio IP
2. SDI Audio IP Getting Started
3. SDI Audio Altera FPGA IP Functional Description
4. SDI Audio Altera FPGA IP Parameters
5. SDI Audio Altera FPGA IP Interface Signals
6. SDI Audio Altera FPGA IP Registers
7. SDI Audio IP User Guide Archives
8. Document Revision History for the SDI Audio IP User Guide

5.5. SDI Audio IP Register Interface Signals

All SDI Audio IP cores use the same register interface signals.

Table 25.  SDI Audio IP Register Interface SignalsThe register interface is a standard 8-bit wide Avalon® memory-mapped interface agent.
Signal Width Direction Description
reg_clk [0:0] Input Clock for the Avalon® memory-mapped interface register interface.
reg_reset [0:0] Input Reset for the Avalon® memory-mapped interface register interface.
reg_base_addr [5:0] Input Reset for the Avalon® memory-mapped interface register interface.
reg_burst_count [5:0] Input Transfer size in bytes.
reg_waitrequest [0:0] Output Wait request.
reg_write [7:0] Input Write request.
reg_writedata [0:0] Input Data to be written to target.
reg_read [0:0] Input Read request.
reg_readdatavalid [0:0] Output Requested read data valid after read latency.
reg_readdata [7:0] Output Data read from target.
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