5.2. SDI Audio Extract Signals
The following tables list the signals for the SDI Audio Extract IP core.
This table lists the clock recovery input and output signals.
| Signal |
Width |
Direction |
Description |
|---|---|---|---|
| reset | [0:0] |
Input |
This signal resets the system. |
| fix_clk | [0:0] |
Input |
Assert this 200 MHz reference clock when you turn on the Include Clock parameter. If you do not turn on the Include Clock parameter, tie this signal low. |
| aud_clk_out | [0:0] |
Output |
The core asserts this 64 × sample rate clock (3.072 MHz audio clock) when you turn on the Include Clock parameter. You use this clock to clock the audio interface in synchronous mode. As the core creates this clock digitally, it is prone to higher levels of jitter. |
| aud_clk48_out | [0:0] |
Output |
The core asserts this sample rate clock when you turn on the Include Clock parameter. |
| aud_z | [0:0] |
Output |
The core asserts this signal to indicate the Z preamble. |
This table lists the video input signals.
| Signal |
Width |
Direction |
Description |
|---|---|---|---|
| vid_clk | [0:0] |
Input |
The video clock that is typically 27 MHz for SD-SDI, 74.25 MHz or 74.17 MHz for HD-SDI, or 148.5 MHz or 148.35 MHz for 3G-SDI standards. You can use higher clock rates with the vid_datavalid signal. |
| vid_std | [1:0] |
Input |
Indicates the received video standard. Applicable for 3G-SDI, dual standard, and triple standard modes only. Set this signal to indicate the following formats:
|
| vid_datavalid | [0:0] |
Input |
Assert this signal when the video data is valid. |
| vid_data | [19:0] |
Input |
This signal carries luma and chroma information. SD-SDI:
HD-SDI and 3G-SDI Level A:
3G-SDI Level B:
|
| vid_locked | [0:0] |
Input |
Assert this signal when the video is locked. |
This table lists the audio input and output signals.
| Signal |
Width |
Direction |
Description |
|---|---|---|---|
| aud_clk | [0:0] |
Input |
Set this clock to 3.072 MHz that is synchronous to the extracted audio. For SD-SDI inputs, this mode of operation limits the core to extracting audio that is synchronous to the video. For HD-SDI inputs, you must generate this clock from the optional 48 kHz output or the audio must be synchronous to the video. |
| aud_ws_in | [0:0] |
Input |
Some audio receivers provide a word select output to align the serial outputs of several audio extract cores. In these circumstances, assert this signal to control the output timing of the audio extract externally, otherwise set it to 0. This signal must be a repeating cycle of high for 32 aud_clk cycles followed by low for 32 aud_clk cycles. |
| aud_de | [0:0] |
Output |
Assert this data enable signal to indicate valid information on the aud_ws and aud_data signals. In synchronous mode, the core ignores this signal. The core asserts this data enable signal to indicate valid information on the aud_ws and aud_data signals. In synchronous mode, the core drives this signal high. |
| aud_ws | [0:0] |
Output |
The core asserts this word select signal to provide framing for deserialization and to indicate left or right sample of channel pair. |
| aud_data | [0:0] |
Output |
The core asserts this signal to extract the internal AES audio signal from the AES output module. In parallel mode, this signal is 32 bits wide. |
| [31:0] |
Output |
This table lists the Avalon-ST audio signals when you instantiate the SDI Audio Extract IP core in Platform Designer (Standard).
| Signal |
Width |
Direction |
Description |
|---|---|---|---|
| aud(n)_clk | [0:0] |
Input |
Clocked audio clock. All the audio input signals are synchronous to this clock. |
| aud(n)_ready | [0:0] |
Output |
Avalon-ST ready signal. Assert this signal when the device is able to receive data. |
| aud(n)_valid | [0:0] |
Input |
Avalon-ST valid signal. The core asserts this signal when it receives data. |
| aud(n)_sop | [0:0] |
Input |
Avalon-ST start of packet signal. The core asserts this signal when it is starting a new frame. |
| aud(n)_eop | [0:0] |
Input |
Avalon-ST end of packet signal. The core asserts this signal when it is ending a frame. |
| aud(n)_channel | [7:0] |
Input |
Avalon-ST select signal. Use this signal to select a specific channel. |
| aud(n)_data | [23:0] |
Input |
Avalon-ST data bus. This bus transfers data. |
This table lists the direct control interface signals. The direct control interface is internal to the SDI Audio Extract IP core.
| Signal |
Width |
Direction |
Description |
|---|---|---|---|
| reg_clk | [0:0] |
Input |
Clock for the direct control interface. |
| audio_control | [7:0] |
Input |
This signal does the same function as the audio control register. |
| audio_presence | [7:0] |
Input |
This signal does the same function as the audio presence register. |
| audio_status | [7:0] |
Output |
This signal does the same function as the audio status register. |
| sd_edp_presence | [7:0] |
Output |
This signal does the same function as the SD EDP presence register. |
| error_status | [7:0] |
Output |
This signal does the same function as the error status register. |
| error_reset | [15:0] |
Input |
Set any bit of this port high for a single cycle of reg_clk to clear the corresponding bit of the error_status signal. Setting any of bits [3:0] high for a clock cycle resets the entire 4-bit error counter. |
| fifo_status | [7:0] |
Input |
This signal does the same function as the FIFO status register. |
| fifo_reset | [7:0] | Input | Set high for a single cycle of reg_clk to clear the underflow or overflow field of the fifo_status signal. |
| clock_status | [7:0] | Input | This signal does the same function as the clock status register. |
| csram_addr | [5:0] | Input | Channel status RAM address. The contents of the selected address are valid on the csram_data signal after one cycle of reg_clk. |
| csram_data | [7:0] | Input | Channel status data. This signal does the same function as the channel status RAM. |