SDI Audio Intel FPGA IP User Guide

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ID 683333
Date 6/21/2022
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Document Table of Contents
Document Table of Contents x
1. SDI Audio Intel FPGA IP Overview 2. SDI Audio Intel FPGA IP Getting Started 3. SDI Audio Intel FPGA IP Functional Description 4. SDI Audio Intel FPGA IP Parameters 5. SDI Audio Intel FPGA IP Interface Signals 6. SDI Audio Intel FPGA IP Registers 7. SDI Audio Intel FPGA IP User Guide Archives 8. Document Revision History for the SDI Audio Intel FPGA IP User Guide
1. SDI Audio Intel FPGA IP Overview x
1.1. Release Information
2. SDI Audio Intel FPGA IP Getting Started x
2.1. Instantiating the SDI Audio Intel FPGA IP Simulating the Testbench
3. SDI Audio Intel FPGA IP Functional Description x
3.1. SDI Audio Embed IP Core 3.2. SDI Audio Extract IP Core 3.3. SDI Clocked Audio Input IP Core 3.4. SDI Clocked Audio Output IP Core 3.5. AES Format 3.6. Avalon-ST Audio Interface
4. SDI Audio Intel FPGA IP Parameters x
4.1. SDI Audio Embed Parameters 4.2. SDI Audio Extract Parameters 4.3. SDI Audio Clocked Audio Input Parameters 4.4. SDI Audio Clocked Audio Output Parameters
5. SDI Audio Intel FPGA IP Interface Signals x
5.1. SDI Audio Embed Signals 5.2. SDI Audio Extract Signals 5.3. SDI Audio Clocked Input Signals 5.4. SDI Audio Clocked Output Signals 5.5. SDI Audio IP Register Interface Signals
6. SDI Audio Intel FPGA IP Registers x
6.1. SDI Audio Embed Registers 6.2. SDI Audio Extract Registers 6.3. SDI Clocked Audio Input Registers 6.4. SDI Clocked Audio Output Registers
1. SDI Audio Intel FPGA IP Overview
2. SDI Audio Intel FPGA IP Getting Started
3. SDI Audio Intel FPGA IP Functional Description
4. SDI Audio Intel FPGA IP Parameters
5. SDI Audio Intel FPGA IP Interface Signals
6. SDI Audio Intel FPGA IP Registers
7. SDI Audio Intel FPGA IP User Guide Archives
8. Document Revision History for the SDI Audio Intel FPGA IP User Guide

6.2. SDI Audio Extract Registers

The following tables list the registers for the SDI Audio Extract IP core.

Table 27.  SDI Audio Extract Register Map

Bytes Offset

Name

00h

Audio Control Register

01h

Audio Presence Register

02h

Audio Status Register

03h

SD EDP Presence Register

04h

Error Status Register

05h

Reserved

06h

FIFO Status Register

07h

Clock Status Register

08h-09h

Reserved

10h-3Fh

Channel Status RAM (0×00), (0×01), ... (0×2F)

Table 28.  SDI Audio Extract Registers

Bit

Name

Access

Description

Audio Control Register

0

Enable

RW

Enables the audio extraction component and internal AES output.

3:1

Extract pair

RW

Defines the audio pair that the component extracts. For example:

  • [000] = Extract the first channel pair of audio signal
  • [111] = Extract the eighth channel pair of audio signal

4

Extract pair MSB

RW

For 3G-SDI Level A standard, this field extends the extract pair field to allow for future implementations with 32 embedded audio channels.

For 3G-SDI Level B standard, this field selects the active video half of the 3G multiplex.

5

Mute

RW

Drive this register high to mute the audio output.

7:6

Unused

—

Reserved for future use.

Audio Presence Register

3:0

Data packet present

RO

Reports which audio data groups are detected in the SDI stream.

The following bits correspond to the number of audio groups detected:

  • Bit [0] = Audio group 1
  • Bit [1] = Audio group 2
  • Bit [2] = Audio group 3
  • Bit [3] = Audio group 4

7:4

Control packet present

RO

Reports which audio control packets are detected in the SDI stream.

Audio Status Register

3:0

Active channel

RO

Reflects the lower four bits of the active channel field of the audio control packet.

4

Asynchronous

RO

Reflects the asx bit (synchronous mode bit) of the RATE (sampling rate) field of the audio control packet.

6:5

Sample rate

RO

Reports the X1 and X0 bits of the sample rate code from the RATE field of the audio control packet.

7

Status valid

RO

Set to 1b when the audio control packet is present in the video stream.

SD EDP Presence Register

3:0

EDP Present

RO

Reports which audio extended data groups are detected in the SD-SDI stream.

7:4

Unused

—

Reserved for future use.

Error Status Register

3:0

Error counter

RW

Counts up to 15 errors since last reset. Write 1b to any bit of this field to reset the entire counter to zero.

4

Ancillary CS fail

RW

Indicates that an error has been detected in the ancillary packet checksum. This bit stays set until cleared by writing 1b to this register.

5

Ancillary parity fail

RW

Indicates that an error has been detected in at least one of the parity fields:
  • ancillary packet parity bit
  • audio sample parity bit (for SD-SDI)
  • AES sample parity bit (for HD-SDI
This bit stays set until cleared by writing 1b to this register.

6

Channel status CRC fail

RW

Indicates that an error has been detected in the channel status CRC. This bit stays set until cleared by writing 1b to this register.

7

Audio packet ECRC fail

RW

Indicates that an error has been detected in the ECRC that forms part of the HD audio data packet. This bit stays set until cleared. To clear, write 1b to this register.

FIFO Status Register

6:0

FIFO fill level

RO

Reports the amount of data in either the audio output FIFO or the Avalon-ST audio FIFO when the optional Avalon-ST Audio interface is used.

7

Overflow/underflow

RW

This register bit goes high if one of the following occurs (based on the output mode used):

  • underflow or overflow of the audio output FIFO
  • overflow of the Avalon-ST audio FIFO
This register always goes high at the beginning, so you must clear the audio FIFO first for the register to indicate underflow or overflow.

Clock Status Register

4:0

Offset

RO

Defines the frequency of the generated audio.

6:5

Unused

—

Reserved for future use.

7

74.17-MHz video clock

RO

To create a 48-kHz signal synchronous to the video clock, you must detect whether a 1 or 1/1.001 video clock rate is used. If you detect a 1/1.001 video clock rate, this field returns high.

Channel Status RAM

7:0

Channel status data

WO

Read accesses within the address range 10h to 3Fh to the channel status RAM. This field returns the 24 bytes of channel status for X channel starting at address 10h, and the 24 bytes of channel status for Y channel starting at address 28h.

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