Intel® Arria® 10 GX/GT Device Errata and Design Recommendations

Download PDF
ID 683331
Date 8/03/2022
Public
Document Table of Contents
Document Table of Contents x
1. About this Document
1. About this Document x
1.1. Design Recommendations for Intel® Arria® 10 GX/GT Devices 1.2. Device Errata for Intel® Arria® 10 GX/GT Devices 1.3. Document Revision History for Intel® Arria® 10 GX/GT Device Errata and Design Recommendations
1.1. Design Recommendations for Intel® Arria® 10 GX/GT Devices x
1.1.1. Intel® Arria® 10 Device Lifetime Guidance
1.1.1. Intel® Arria® 10 Device Lifetime Guidance x
1.1.1.1. Design Recommendation
1.2. Device Errata for Intel® Arria® 10 GX/GT Devices x
1.2.1. Automatic Lane Polarity Inversion for PCIe Hard IP 1.2.2. Link Equalization Request Bit in the PCIe Hard IP Cannot Be Cleared by Software 1.2.3. High VCCBAT Current when VCC is Powered Down Workaround Status 1.2.4. Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR) 1.2.5. GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation
1. About this Document

1.2.3. High VCCBAT Current when VCC is Powered Down

If you power off VCC when VCCBAT remains powered on, VCCBAT may draw higher current than expected.

If you use the battery to maintain volatile security keys when the system is not powered up, VCCBAT current could be up to 120 µA, resulting in shortened battery life.

Workaround

Contact your battery provider to evaluate the impact to the retention period of the battery used on your board.

There is no impact if you connect the VCCBAT to the on-board power rail.

Status

Affects: Intel® Arria® 10 GX/GT devices

Status: No planned fix.

Level Two Title