Intel® Arria® 10 GX/GT Device Errata and Design Recommendations

Download PDF
ID 683331
Date 8/03/2022
Public
Document Table of Contents
Document Table of Contents x
1. About this Document
1. About this Document x
1.1. Design Recommendations for Intel® Arria® 10 GX/GT Devices 1.2. Device Errata for Intel® Arria® 10 GX/GT Devices 1.3. Document Revision History for Intel® Arria® 10 GX/GT Device Errata and Design Recommendations
1.1. Design Recommendations for Intel® Arria® 10 GX/GT Devices x
1.1.1. Intel® Arria® 10 Device Lifetime Guidance
1.1.1. Intel® Arria® 10 Device Lifetime Guidance x
1.1.1.1. Design Recommendation
1.2. Device Errata for Intel® Arria® 10 GX/GT Devices x
1.2.1. Automatic Lane Polarity Inversion for PCIe Hard IP Workaround Status 1.2.2. Link Equalization Request Bit in the PCIe Hard IP Cannot Be Cleared by Software 1.2.3. High VCCBAT Current when VCC is Powered Down 1.2.4. Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR) 1.2.5. GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation
1. About this Document

1.2.1. Automatic Lane Polarity Inversion for PCIe Hard IP

For Intel® Arria® 10 PCIe Hard IP open systems where you do not control both ends of the PCIe link, Intel does not guarantee automatic lane polarity inversion with the Gen1x1 configuration, Configuration via Protocol (CvP), or Autonomous Hard IP mode. The link may not train successfully, or it may train to a smaller width than expected. There is no planned workaround or fix.

For all other configurations, refer to the following workaround.

Workaround

Refer to the Knowledge Database for details to workaround this issue.

Status

Affects: Intel® Arria® 10 GX/GT devices.

Status: No planned fix.

Related Information
Level Two Title