Intel® Arria® 10 GX/GT Device Errata and Design Recommendations

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ID 683331
Date 8/03/2022
Public
Document Table of Contents
Document Table of Contents x
1. About this Document
1. About this Document x
1.1. Design Recommendations for Intel® Arria® 10 GX/GT Devices 1.2. Device Errata for Intel® Arria® 10 GX/GT Devices 1.3. Document Revision History for Intel® Arria® 10 GX/GT Device Errata and Design Recommendations
1.1. Design Recommendations for Intel® Arria® 10 GX/GT Devices x
1.1.1. Intel® Arria® 10 Device Lifetime Guidance
1.1.1. Intel® Arria® 10 Device Lifetime Guidance x
1.1.1.1. Design Recommendation
1.2. Device Errata for Intel® Arria® 10 GX/GT Devices x
1.2.1. Automatic Lane Polarity Inversion for PCIe Hard IP 1.2.2. Link Equalization Request Bit in the PCIe Hard IP Cannot Be Cleared by Software 1.2.3. High VCCBAT Current when VCC is Powered Down 1.2.4. Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR) 1.2.5. GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation
1. About this Document

1.2. Device Errata for Intel® Arria® 10 GX/GT Devices

The table below lists specific device issues and affected Intel® Arria® 10 GX/GT devices.
Table 2.  Device Issues
Issue Affected Devices Planned Fix
Automatic Lane Polarity Inversion for PCIe Hard IP All Intel® Arria® 10 GX/GT devices No planned fix
Link Equalization Request Bit in the PCIe Hard IP Cannot Be Cleared by Software All Intel® Arria® 10 GX/GT devices No planned fix
High VCCBAT Current when VCC is Powered Down All Intel® Arria® 10 GX/GT devices No planned fix
Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR)
  • Intel® Arria® 10 GX 160 devices
  • Intel® Arria® 10 GX 220 devices
  • Intel® Arria® 10 GX 270 devices
  • Intel® Arria® 10 GX 320 devices
No planned fix
GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation
  • Intel® Arria® 10 GX 160 devices
  • Intel® Arria® 10 GX 220 devices
  • Intel® Arria® 10 GX 270 devices
  • Intel® Arria® 10 GX 320 devices
  • Intel® Arria® 10 GX 480 devices
  • Intel® Arria® 10 GX 570 devices
  • Intel® Arria® 10 GX 660 devices
No planned fix

Section Content
Automatic Lane Polarity Inversion for PCIe Hard IP
Link Equalization Request Bit in the PCIe Hard IP Cannot Be Cleared by Software
High VCCBAT Current when VCC is Powered Down
Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR)
GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation

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