Intel® Quartus® Prime Design Suite Version 18.1 Update Release Notes

Download PDF
ID 683328
Date 4/17/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Quartus® Prime Design Suite Version 18.1 Update Release Notes 2. Issues Addressed in Update 1 3. Issues Addressed in Update 2 4. Software Issues Resolved 5. Software Patches Included in Update Releases 6. Known Issues and Workarounds A. Document Revision History for Intel® Quartus® Prime Design Suite Update Release Notes
2. Issues Addressed in Update 1 x
2.1. Intel® Quartus® Prime Pro Edition Software 2.2. Intel® Quartus® Prime Standard Edition Software 2.3. IP and IP Cores 2.4. DSP Builder for Intel® FPGAs 2.5. Intel High Level Synthesis Compiler 2.6. Intel FPGA SDK for OpenCL*
3. Issues Addressed in Update 2 x
3.1. Intel® Quartus® Prime Pro Edition Software 3.2. IP and IP Cores 3.3. Intel FPGA SDK for OpenCL
1. Intel® Quartus® Prime Design Suite Version 18.1 Update Release Notes
2. Issues Addressed in Update 1
3. Issues Addressed in Update 2
4. Software Issues Resolved
5. Software Patches Included in Update Releases
6. Known Issues and Workarounds
A. Document Revision History for Intel® Quartus® Prime Design Suite Update Release Notes

2.4. DSP Builder for Intel® FPGAs

Unless stated otherwise, the following DSP Builder for Intel® FPGAs issues apply only to the Intel® Quartus® Prime Pro Edition software.

  • Single-precision floating-point adders in a DSP Builder design can now use a mixture of hard and soft implementations.
  • VFFT_btb and VFFT_Light_btb blocks have been added. These support back-to-back operation of the variable-size FFT, so there is no need to flush the FFT pipeline between different-size FFT iterations.
  • A defect in the VFFT_cp_btb and VFFT_Light_cp_btb blocks has been corrected. When the 18.1 versions of these blocks were used with multiple subchannels, the output start-of-packet, size and (for VFFT_cp_btb) end-of-packet signals were not correctly synchronized with the output valid signal.
  • The optimization of floating-point scalar products is now slightly less aggressive. With default settings, DSP Builder no longer attempts to infer a chain-in input for scalar products. As a result of this change, complex scalar products now consume slightly more DSP blocks but require fewer logic resources for latency-balancing.
  • Fixed initialization of SharedMems of type single precision float.
  • Added support for loop blocks to the Advanced C-model feature.
Level Two Title