AN 824: Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide

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ID 683312
Date 8/08/2017
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Document Table of Contents
Document Table of Contents x
Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide
Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide x
OpenCL BSP Compilation Flow OpenCL BSP Floorplan Partition Guidelines for OpenCL BSP Floorplanning Guidelines for Maximum Operating Frequency Guidelines for Evaluating BSP Resource Utilization Efficiency Document Revision History
Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide

OpenCL BSP Floorplan Partition

OpenCL BSP floorplan is mainly divided into the following two regions:
  • Static region: Represents the region having BSP related hardware that remains static. The timing is closed for this region during base compilation. In general, the goal is to minimize the chip resources used by this region to close timing.
  • Kernel region: Represents the partial reconfiguration (PR) region that is reserved for freeze_wrapper_inst|kernel_system_inst module, which contains the kernel. In general, the goal is to reserve chip resources to a maximum extent for this region.
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