AN 824: Intel® FPGA SDK for OpenCL™ Board Support Package Floorplan Optimization Guide

ID 683312
Date 8/08/2017
Public

Guidelines for Evaluating BSP Resource Utilization Efficiency

The higher the resource utilization percentage, the better the area utilization in the static area of your BSP. A high resource utilization percentage also implies that more resources are available for the kernel region.
Follow the steps below to calculate the resource utilization percentage of your BSP:
  1. Obtain values for all resources in the FPGA from the top.fit.rpt or base.fit.rpt available under the Partition Statistics section of the Fitter report.
  2. Deduct the value for "freeze_wrapper_inst|kernel_system_inst" (kernel region).
Tip: Focus more on the values of adaptive logic module (ALM) than on the values of other resources. Ensure that the resource utilization percentage for ALM is closer to the OpenCL reference BSP. A very high percentage for ALM might lead to congestion, which can increase the compilation time and introduce routing congestions in complex kernels. However, you can always increase or decrease the static region area, and observe the compilation time and fmax.

The following table reflects the OpenCL BSP resource utilization of Arria® 10 GX devices in the 17.0 release.

Table 1.  OpenCL BSP Resource Utilization of Intel Arria® 10 GX devices in the 17.0 Release
  Total Available Reserved for Kernel Available for BSP Used by BSP %
ALM 427200 393800 33400 23817.5 71.31%
Registers 1708800 1575200 133600 38913 29.13%
M20K 2713 2534 179 134 74.86%
DSP 1518 1518 0 0 N/A

Observe that the floorplanning is executed in such a way that the static region will not have any DSP blocks.