R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* IP Core Release Notes

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Date 10/07/2024
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1. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core Release Notes
1. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core Release Notes x
1.1. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v11.4.0 1.2. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v11.3.0 1.3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v11.2.0 1.4. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v11.1.0 1.5. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v11.0.0 1.6. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v10.0.0 1.7. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v9.0.0 1.8. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP core v8.0.0 1.9. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v7.0.0 1.10. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v6.0.0 1.11. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v5.0.0 1.12. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v4.0.0 1.13. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v3.0.0 1.14. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v2.0.0 1.15. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v1.0.0 1.16. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v1.0.0 1.17. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express User Guide Archives
1. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core Release Notes

1.13. R-Tile IP for PCI Express IP Core v2.0.0

Table 25.  v2.0.0 2021.06.23
Quartus® Prime Version Description Impact
21.2 Added support for the Completion Timeout feature in TLP Bypass mode to the R-tile Avalon® Streaming IP. Completion Timeout is now supported for all modes (Endpoint, Root Port and TLP Bypass).
Added the pin_perst_n_o output port to the IP. This output is derived from the pin_perst_n input to the R-tile IP for PCIe, and it can be used by the application logic in the FPGA fabric.
Added support for the QuestaSim simulator for the PCIe mode. You can now simulate the R-tile PCIe IP using the QuestaSim simulator.
Added support for the x8x8 design example. You can now generate a PIO design example in the x8x8 configuration.
Table 26.  R-tile Avalon Streaming IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported.
Configuration PCIe IP Support Timing Support
EP RP BP -1 -2 -3
16-channel PIPE Direct SCT SCT SCT 500 MHz 500 MHz N/A
Gen5 x16 1024-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x16 1024-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x16 1024-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen5 x8/x8 512-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x8/x8 512-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x8/x8 512-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen5 x4/x4/x4 256-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x4/x4/x4 256-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x4/x4/x4 256-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
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