R-Tile Avalon® Streaming FPGA IP for PCI Express* IP Core Release Notes

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Date 8/04/2025
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1. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core Release Notes
1. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core Release Notes x
1.1. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v12.0.0 1.2. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v11.6.0 1.3. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v11.5.0 1.4. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v11.4.0 1.5. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v11.3.0 1.6. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v11.2.0 1.7. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v11.1.0 1.8. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v11.0.0 1.9. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v10.0.0 1.10. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v9.0.0 1.11. R-Tile Avalon® Streaming FPGA IP for PCI Express IP core v8.0.0 1.12. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v7.0.0 1.13. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v6.0.0 1.14. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v5.0.0 1.15. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v4.0.0 1.16. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v3.0.0 1.17. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v2.0.0 1.18. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v1.0.0 1.19. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v1.0.0 1.20. R-Tile Avalon® Streaming FPGA IP for PCI Express User Guide Archives
1. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core Release Notes

1.16. R-Tile Avalon® Streaming FPGA IP for PCI Express IP Core v3.0.0

Table 31.  v3.0.0 2021.10.04
Quartus® Prime Version Description Impact
21.3 Added design example support for the Agilex™ 7 I-Series Development Kit. You can generate the 1x16 design example targeting the Agilex™ 7 I-Series Development Kit for early evaluation. Note that the Debug Toolkit is not available and is planned to be released in a future release of the IP.
Added support to enable ECRC and LCRC error counters. Improved error telemetry capabilities by allowing the counting of ECRC and LCRC errors on a PCIe link.
Table 32.  R-tile Avalon Streaming IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported.
Configuration PCIe IP Support Timing Support
EP RP BP -1 -2 -3
16-channel PIPE Direct SCT SCT SCT 500 MHz 500 MHz N/A
Gen5 x16 1024-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x16 1024-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x16 1024-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen5 x8/x8 512-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x8/x8 512-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x8/x8 512-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen5 x4/x4/x4 256-bit SCT SCT SCT 500 MHz 500 MHz N/A
Gen4 x4/x4/x4 256-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
Gen3 x4/x4/x4 256-bit SCT SCT SCT 300 MHz 300 MHz 300 MHz
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