R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* IP Core Release Notes

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ID 683311
Date 10/07/2024
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1. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core Release Notes
1. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core Release Notes x
1.1. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v11.4.0 1.2. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v11.3.0 1.3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v11.2.0 1.4. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v11.1.0 1.5. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v11.0.0 1.6. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v10.0.0 1.7. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v9.0.0 1.8. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP core v8.0.0 1.9. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v7.0.0 1.10. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v6.0.0 1.11. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v5.0.0 1.12. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v4.0.0 1.13. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v3.0.0 1.14. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v2.0.0 1.15. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v1.0.0 1.16. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core v1.0.0 1.17. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express User Guide Archives
1. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP Core Release Notes

1.2. R-Tile IP for PCI Express IP Core v11.2.0

Table 3.  v11.2.0 2024.04.01
Quartus® Prime Version Description Impact
24.1

Added support for the Performance Design Example for TLP Bypass mode.

The Performance Design Example can be generated in the IP Parameter Editor targeting the Agilex™ 7 I-Series Development Kit for Gen5x16 TLP Bypass upstream mode. Simulation support is not available in the current Quartus® Prime release.

Table 4.  R-tile Avalon Streaming IP for PCIe Support Matrix for Agilex™ 7 DevicesEP = Endpoint, RP = Root Port, BP = TLP Bypass. Support level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported.
Configuration PCIe IP Support Timing Support
EP RP BP UP/DN -1 -2 -3
16-channel PIPE Direct N/A N/A N/A 500 MHz 500 MHz N/A
Gen5 x16 1024-bit SCTH SCTH SCTH 500 MHz 500 MHz N/A
Gen4 x16 1024-bit SCTH SCTH SCTH 300 MHz 300 MHz 300 MHz
Gen3 x16 1024-bit SCTH SCTH SCTH 300 MHz 300 MHz 300 MHz
Gen4 x16 512-bit (*) SCTH SCTH SCTH 500 MHz 500 MHz N/A
Gen3 x16 512-bit (*) SCTH SCTH SCTH 500 MHz 500 MHz N/A
Gen5 x8/x8 512-bit SCTH SCTH SCTH 500 MHz 500 MHz 450 MHz
Gen4 x8/x8 512-bit SCTH SCTH SCTH 300 MHz 300 MHz 300 MHz
Gen3 x8/x8 512-bit SCTH SCTH SCTH 300 MHz 300 MHz 300 MHz
Gen4 x8/x8 256-bit (*) SCTH SCTH SCTH 500 MHz 500 MHz N/A
Gen3 x8/x8 256-bit (*) SCTH SCTH SCTH 300 MHz 300 MHz 300 MHz
Gen5 x4/x4/x4/x4 256-bit SCTH SCTH SCTH 500 MHz 500 MHz N/A
Gen4 x4/x4/x4/x4 256-bit SCTH SCTH SCTH 500 MHz 500 MHz N/A
Gen3 x4/x4/x4/x4 256-bit SCTH SCTH SCTH 300 MHz 300 MHz 300 MHz
Gen4 x4/x4/x4/x4 128-bit (*) SCTH SCTH SCTH 500 MHz 500 MHz N/A
Gen3 x4/x4/x4/x4 128-bit (*) SCTH SCTH SCTH 300 MHz 300 MHz 300 MHz
Note:
(*) These configurations are only available in Production devices or Engineering Samples with the following OPNs:
  • AGIx027R29AxxxxR2
  • AGIx027R29AxxxxR3
  • AGIx027R29BxxxxR3
  • AGIx023R18AxxxxR0
  • AGIx041R29DxxxxR0
  • AGIx041R29DxxxxR1
For additional details on OPN decoding, refer to Agilex™ 7 FPGAs and SoCs Device Overview.
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