JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

ID 683298
Date 10/14/2022
Document Table of Contents

1.2.6. Clocking Scheme

The main reference clock for the design example is device_clk. This clock must be supplied from an external source. The device_clk is the reference clock for the core PLL, ATX PLL and the TX/RX transceiver PHY. The core PLL generates the link_clk and frame_clk from device_clk. The link_clk clocks the JESD204B IP core link layer and link interface of the transport layer. The frame_clk clocks the transport layer, test pattern generator and checker modules, and any downstream modules. An external source supplies a clock called the mgmt_clk to clock the Avalon® memory-mapped interfaces of Platform Designer components.

Table 13.  System Clocking for the Design Example
Clock Description Source Modules Clocked
device_clk Reference clock for the core PLL, ATX PLL, and RX transceiver PHY External Core PLL, ATX PLL, RX transceiver PHY
link_clk Link layer clock device_clk JESD204B IP core link layer, transport layer link interface
frame_clk Frame layer clock device_clk Transport layer, test pattern generator and checker, downstream modules
mgmt_clk Control plane clock External Avalon® memory-mapped interfaces