Intel® Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 6/26/2023
Public

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MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE

Allows you to specify whether you want the Timing Analyzer to evaluate timing constraints between the write and the read operation of the MLAB memory block. Performing a write and read operation simultaneously at the same address might result in metastability because no timing constraints between those operations exist by default. Turning on this option introduces timing constraints between the write and read operation on the MLAB memory block and thereby avoids metastability issues; however, turning on this option degrades the performance of the MLAB memory blocks. If your design does not perform write and read operations simulataneously at the same address you do not need to set this option.

Type

Boolean

Device Support

  • Intel Agilex® 7
  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX
  • Intel® Stratix® 10

Notes

This assignment supports Fitter wildcards.

This assignment is included in the Fitter report.

This assignment supports synthesis wildcards.

Syntax

set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE -entity <entity name> <value>
set_instance_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE -to <to> -entity <entity name> <value>
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE <value>

Default Value

Off