FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
2.1.1. SDRAM Signals
This table defines the interface for each of the two DDR4 memories from the viewpoint of the AFU.
| Signal Name | Direction (AFU viewpoint) | Width | Description |
|---|---|---|---|
| clk | input | 1 | Provides synchronization for internal logic. |
| waitrequest | input | 1 | Asserts when the EMIF controller is unable to respond to a read or write request. |
| readdata | input | 512 | Read data signal from the DDR4 to the AFU. |
| readdatavalid | input | 1 | Used for variable-latency, pipelined read transfers. When asserted, indicates that the readdata signal contains valid data. |
| burstcount | output | 7 | Used to indicate the number of transfers in each burst. |
| writedata | output | 512 | Write data signal to the external DDR4. |
| address | output | 27 | By default, the interconnect translates the byte address into a word address in the slave’s address space. From the perspective of the slave, each slave access is for a word of data. |
| write | output | 1 | Asserted to indicate a write transfer. |
| read | output | 1 | Asserted to indicate a read transfer. |
| byteenable | output | 64 | Enables one or more specific byte lanes during transfers on interfaces of width greater than 8 bits. Each bit in byteenable corresponds to a byte in writedata and readdata. |