FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
2.1. Memory Interface
The Intel® FPGA PAC with Intel® Arria® 10 GX FPGA features two DDR4 SDRAM memory banks, each of 4 GB capacity. They can be used by the AFU as a local workspace for large datasets. Each bank can be accessed independently by the AFU. Each memory bank interface is 64-bits and operates at 1066 MHz DDR.
| Parameter | Value |
|---|---|
| Memory Protocol | DDR4-SDRAM |
| AFU Interface Type | Avalon™ Memory Mapped Interface ( Avalon® -MM) |
| Number of Memory Interfaces | 2 |
| Density per Memory Interface | 4 GB |
| AFU-Accessible Memory Address Bus Width | 27-bit |
| AFU-accessible Memory Data Width | 512-bit |
| Interface Frequency | 266 MHz |
| Maximum Burst Size | 64 beats |
| Address Mapping | CS-CID-Row-Bank-Col-BG |