FPGA Interface Manager Data Sheet: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683292
Date 8/18/2021
Public

2.4. Reset

Table 5.  Reset Specifications
Subsystem Parameter Value Notes
Resets Min Reset Width 512 pClk cycles Minimum number of pClk clock cycles the FIM holds the AFU in reset.
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