Mailbox Client Intel® FPGA IPs User Guide

Download PDF
ID 683290
Date 7/08/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.5.2. Interrupt Status Register

Use the interrupt_status register to monitor the status of the FIFO and identify invalid commands.

Your logic can poll the error bits of the interrupt_status register. Or, you can configure the EN_COMMAND_INVALID bit of the interrupt enable register to interrupt when an error occurs.

When an error occurs, the Mailbox Client Intel® FPGA IP clears all pending responses. Your logic should not expect any response from Mailbox Client Intel® FPGA IP after an error occurs. Your logic must assert reset for a minimum of 10 clock cycles to reset the Mailbox Client Intel® FPGA IP.

Table 9.  Interrupt Status Register
Bit Fields Access Default Value Description
31:8 Reserved
9 RD_RSP_FIFO_WHEN_EMPTY R 0x0 Read response FIFO when empty detection interrupt.
  • 1: Indicates the Mailbox Client Intel® FPGA IP detected that you attempted an erroneous behavior to read the response FIFO when it is empty which is not allowed. You must reset the Mailbox Client Intel® FPGA IP.
  • 0: Indicates no erroneous behavior to read the response FIFO when it is empty was detected.
8 WR_CMD_FIFO_WHEN_FULL R 0x0 Write command FIFO when full detection interrupt.
  • 1: Indicates the Mailbox Client Intel® FPGA IP detected that you attempted an erroneous behavior to write to the command FIFO when it is full which is not allowed. You must reset the Mailbox Client Intel® FPGA IP.
  • 0: Indicates no erroneous behavior to write the command FIFO when it is full was detected.
7 CRYPTO_ERROR_RECOVERY_PROGRESS 8 R 0x0 Error recovery flow progress interrupt for the cryptographic (crypto) flow.
  • 1: Indicates that the crypto error recovery is in progress. You may use this bit to report the progress of the soft IP error recovery. While in recovery, the SDM is unable to perform read/write operations from the memory.
  • 0: Indicates the crypto error recovery is completed.
6 CRYPTO_MEMORY_TIMEOUT 8 R 0x0 Cryptographic services timer for memory target interrupt. Timeout value is set by Crypto Memory Timeout Value parameter in the Mailbox Client Intel® FPGA IP.
  • 1: Indicates that the timeout occurred in either the memory target write or read path in the AXI transaction. You must reset the Mailbox Client IP (in_reset and axi_in_reset) and your memory target device.
  • 0: No timeout occurred
5 BACKPRESSURE_TIMEOUT R 0x0 SDM backpressure timer interrupt.
  • 1: The SDM backpressure timer has timeout. Indicates that a fatal error occurred in SDM. You must reset the device. To reset, reconfigure or power cycle the device.
  • 0: The SDM backpressure timer has not timeout.
4 EOP_TIMEOUT R 0x0
End of Packet (EOP) timer interrupt.
  • 1: Indicates that the EOP timer has timeout. You must reset the Mailbox Client Intel® FPGA IP.
  • 0: The EOP timer has not timeout.
Indicates that the Mailbox Client Intel® FPGA IP did not receive the full command with EOP due to:
  • Mailbox did not receive the last argument with EOP.
  • Mailbox already received all arguments without the EOP in it.
3 COMMAND_INVALID R 0x0 Invalid command interrupt. Indicates a mismatch between the command length specified in the command header and the number of words sent. Hardware clears this bit.
  • 1: Indicates that the command is invalid. You must reset the Mailbox Client Intel® FPGA IP.
  • 0: The command is valid.
2 Reserved — — Reserved.
1 CMD_FIFO_NOT_FULL R 0x0 Command FIFO is not full interrupt.
  • 1: Indicates command FIFO is not full. The client can drive data.
  • 0: Indicates the FIFO is full.

The FIFO automatically clears this bit. You do not need to clear this bit manually.
0 DATA_VALID R 0x0 Data valid interrupt.
  • 1: Indicates that valid data is available. The master can read.
  • 0: Indicates the FIFO is empty.

The FIFO automatically clears this bit. You do not need to clear this bit manually.
8 The crypto service feature is only available for Agilex™ 7 and Agilex™ 5 devices.
Level Two Title