Writing Command Packet

Write Command Description

When you send a command to the SDM, write the command word into command register, which is the base address. To stay in sync with the hardware, while the command length (t) is greater than zero, write the header and arguments in the Command register which is (base address + 0). Continue writing the header or arguments, one word at the time, in the Command register (base address + 0) while there is available free space in the FIFO for commands (n > t). Write the last word to the Command last word register which is (base address +1). For commands with no arguments, write the header to the Command last word register, (base address +1).

Reading from (base address + 2) shows the remaining available free space in the FIFO for commands. The command FIFO can become full when the SDM is busy. The Mailbox Client Intel® FPGA IP requires 3 clock cycles to update the Command FIFO empty space value. You can begin reading the Command FIFO empty space value 3 clock cycles after writing the command to the IP.

You must check the Command FIFO empty space register, (base address + 2) before proceeding to write into the Command or Command last word registers. The behavior of the Mailbox Client Intel® FPGA IP is undefined if you write to (base address + 0) and (base address + 1) while the FIFO is full. The write data is discarded.

In the above scenario, the Mailbox Client Intel® FPGA IP expects a 3-word response (command header and 2 data words). However, the SDM only returns a one-word response, which is the error response code.

You must send commands in the correct order to the Command or Command last word register, as described in Writing Command Packet. Failure to send commands in the correct order can result in loss of services for all mailbox clients, including the following standalone IP cores:

• Temperature Sensor Intel® FPGA IP
• Voltage Sensor Intel® FPGA IP
• Chip ID Intel® FPGA IP
• Advanced SEU Detection Intel® FPGA IP
• Partial Reconfiguration Controller Intel® FPGA IP
• Partial Reconfiguration External Configuration Controller Intel® FPGA IP

Reading Response Packet

Read Command Description

1. Read (base address + 8) to check if bit 0 of Interrupt status register is 1, to indicate the valid data is available for the master to read. You can poll the Interrupt status register continuously until bit 0 is 1.
2. Read (base address + 6) to check the SOP (start of packet), EOP (end of packet), and the Response FIFO fill level (n).

   To read multiple words, complete the following steps:

   1. If SOP = 1 and EOP = 0, the response has multiple words.
   2. If the Response FIFO fill level (n) is non-zero, the FIFO has valid data.
   3. For example, if you perform a QSPI_READ operation to read 10 words from quad SPI flash, a return value of 0x0000002d indicates that the SDM wrote 11 words to the response FIFO. The 11 words comprise a response header word and 10 data words.
   To read a single word, complete the following steps:

   1. If SOP = 1 and EOP = 1, the response has a single word.
   2. If the Response FIFO fill level is non-zero, the FIFO has valid data.
   3. A return value of 0x00000007 indicates that the SDM wrote a single word to the response FIFO. This single is both the start and end of the single-cycle packet.
3. Read the response header at (base address + 5). The LENGTH value specifies the number of words in the response. Proceed to step 4 if the response error code is zero. The response error code is non-zero for unsuccessful commands. Refer to Error Codes for more information.
4. When the length of the response header (t) is greater than zero (LENGTH > 1) , read (base address + 5) to retrieve the response data. While continuously reading the response data, you must also continuously poll (base address + 6) to check the Response FIFO fill level (n). For the final word of the packet, the Response FIFO fill level (n) and EOP value are expected to be 1 at the same time. You must check for EOP = 1 before proceeding to read the final word from the response data.
   Note:

   If the response FIFO is empty, the return data is undefined. You must check the Interrupt status register to ensure that valid data is available. You must verify that the Response FIFO fill level (n) is non-zero before reading the response data.

   Ensure that you read or flush out the content in the response FIFO before issuing a new command to the mailbox. Continuously sending commands without reading back the valid data from the response FIFO gradually fills the response FIFO. When the response FIFO overflows the SDM freezes.

   If the SDM freezes you must reconfigure the device. The Quartus® Prime software supports device reconfiguration starting in version 19.1. For earlier versions of the Quartus® Prime software, power cycle the device to recover.

Restrictions

1. You can only issue one request and read back the response before issuing a new request to the Mailbox Client Intel® FPGA IP.
2. For Agilex™ 5 devices, only one instantiation of the Agilex™ 5 Mailbox Client Intel® FPGA IP is supported
3. For Stratix® 10 devices, multiple mailbox clients in the form of standalone IP cores may have been used in a design to send different commands. In this case, do not instantiate more than six mailbox clients in your design. For designs requiring more than six mailbox clients, use the Mailbox Client Intel® FPGA IP to replace the following standalone IP cores:
   • Temperature Sensor Intel® FPGA IP
   • Voltage Sensor Intel® FPGA IP
   • Chip ID Intel® FPGA IP
   • Serial Flash Mailbox Client Intel® FPGA IP
   Note: Agilex™ devices do not support these standalone IP cores. Instead, use the Mailbox Client Intel® FPGA IP or Agilex™ 5 Mailbox Client Intel® FPGA IP.