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1.1. Release Information
1.2. Device Family Support
1.3. Parameters
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface
1.6. Commands and Responses
1.7. Specifying the Command and Response FIFO Depths
1.8. Enabling Cryptographic Services
1.9. Using the Intel® FPGA IP
1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples
1.11. Nios® II and Nios® V Processors HAL Driver
1.12. Mailbox Client Intel FPGA IP User Guide Archives
1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
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1. Mailbox Client Intel FPGA IP User Guide
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 24.1 |
The Mailbox Client Intel® FPGA IP 1 is a bridge between a host and the secure device manager (SDM). You use the Mailbox Client Intel® FPGA IP to send commands and receive status from SDM peripheral clients2.
The Mailbox Client defines functions that the SDM runs. The following pre-defined functions are available:
The following block diagram shows how to use the Mailbox Client Intel® FPGA IP in an interactive session. The diagram also emphasizes different ways of communicating with IP through the Host Controller.
Figure 1. Mailbox Client Intel® FPGA IP System Block Diagram
This block diagram includes the following components:
- Host Controller: provides possible ways of accessing the Mailbox Client Intel® FPGA IP. Use any of the specified ways to communicate with the host controller:
- System Console with the JTAG to Avalon® Master Bridge Intel® FPGA IP. The System Console provides a Tcl Console pane that you can use to run the IP functions. The JTAG to Avalon® Master Bridge Intel® FPGA IP translates the commands it receives from the System Console to Avalon® memory-mapped interface format that the Mailbox Client Intel® FPGA IP requires.
- Nios® II processor: sends commands to the Mailbox Client Intel® FPGA IP.
- Custom logic: It sends commands to the Mailbox Client Intel® FPGA IP.
- PCIe* Hard IP
- Ethernet IP
-
Mailbox Client Intel® FPGA IP: drives commands and receives responses from the SDM. This component includes FIFOs with a maximum depth of 1024 entries to store commands and responses. The Mailbox Client Intel® FPGA IP interrupt indicates when the input FIFO is full and when the output FIFO contains valid data. You can size these FIFOs to accommodate the commands the you intend to send.
Intel provides a reference design that uses the System Console and the JTAG master to drive the Mailbox Client Intel® FPGA IP. In the Intel Design Store, search for Agilex™ 7 FPGA - Mailbox Client Design Example with QSPI flash Access and Remote System Update to view the design.
Section Content
Release Information
Device Family Support
Parameters
Mailbox Client Intel FPGA IP Core Interface Signals
Mailbox Client Intel FPGA IP Avalon Memory-Mapped Interface
Commands and Responses
Specifying the Command and Response FIFO Depths
Enabling Cryptographic Services
Using the Intel FPGA IP
Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples
Nios II and Nios V Processors HAL Driver
Mailbox Client Intel FPGA IP User Guide Archives
Document Revision History for the Mailbox Client Intel FPGA IP User Guide
Related Information
1 To obtain specific IP names covered by this document, refer to the Release Information section of this document.
2 For the full list of supported SDM-based devices, refer to the Device Family Support section of this document.