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1.1. Release Information
1.2. Device Family Support
1.3. Parameters
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface
1.6. Commands and Responses
1.7. Specifying the Command and Response FIFO Depths
1.8. Enabling Cryptographic Services
1.9. Using the Intel® FPGA IP
1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples
1.11. Nios® II and Nios® V Processors HAL Driver
1.12. Mailbox Client Intel FPGA IP User Guide Archives
1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
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1.4. Mailbox Client Intel® FPGA IP Core Interface Signals
The host communicates with the Mailbox Client Intel® FPGA IP over its Avalon® memory-mapped interface.
Through the AXI manager interface, the crypto service has access to the lowest 1GB of memory, with a maximum data size of 512 MB per each read and write operation.
Note: For Agilex™ 7 and Agilex™ 5 devices, the AXI manager interface is available if you enabled the Enable Crypto Service parameter.
The following figure illustrates the Mailbox Client Intel® FPGA IP interfaces.
Figure 2. Mailbox Client Intel® FPGA IP InterfacesThe AXI manager interface is only available in the Agilex™ 7 and Agilex™ 5 devices with the Enable Crypto Service parameter enabled.
Note: For information about the AXI manager interface, refer to the AXI Manager Interface table.
Note: The avmm_waitrequest signal is mandatory in Quartus® Prime software version 23.2 or later.