F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 683287
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit 3.8. Analog Parameters
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

3.2.1. Traffic Generator

The traffic generator generates traffic in a deterministic format to verify that data is transmitted correctly across the link. The traffic consists of sets of sample words, one for each lane on the link, that the traffic checker transmits to the source user interface.

If you configure the F-Tile Serial Lite IV IP in full mode, the traffic generator also asserts the tx_is_usr_cmd signal at random to specify the packet is from user data for testing purposes. The F-Tile Serial Lite IV IP asserts the num_valid_bytes_eob control signal to signify the number of valid bytes of the burst packet.

Figure 6. Traffic Generator Sample Word FormatThis figure shows the format of the sample words generated for each lane.
Table 9.  Traffic Generator Sample Word Fields

Field

Bits

Description

Word ID

63–59

Contains a static value to distinguish which 64-bit word on the user interface that this sample was presented on. The Word ID value ranges from 0 to (lanes – 1).

Burst Count

58–32

Tracks the number of bursts used to transfer the sample data. This field value starts with one after reset and is incremented each time the start_of_burst signal asserts on the source user interface.

Word Count

31–0

Tracks the number of valid sample words that the traffic generator transfers, across all bursts, to the source user interface.

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