F-Tile CPRI PHY Intel® FPGA IP User Guide

Download PDF
ID 683284
Date 8/15/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the F-Tile CPRI PHY Intel® FPGA IP 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. IP Registers 6. F-Tile CPRI PHY Intel FPGA IP User Guide Archives 7. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide
1. About the F-Tile CPRI PHY Intel® FPGA IP x
1.1. Supported Features 1.2. Block Diagram 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. F-Tile CPRI PHY IP Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
3. IP Parameter Settings x
3.1. Analog Parameters for F-Tile IPs
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency 4.2.2. Calculation for 64b/66b Datapath
1. About the F-Tile CPRI PHY Intel® FPGA IP
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. IP Registers
6. F-Tile CPRI PHY Intel FPGA IP User Guide Archives
7. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

4.1. Reset Logic

There are three main user accessible reset ports:
  • i_tx_rst_n—resets the TX datapath.
  • i_rx_rst_n—resets the RX datapath.
  • i_reconfig_reset—resets the Avalon® memory-mapped interface connections to PCS + PMA CSRs, and soft IP CSR.
Figure 13. Reset Block Diagram
Level Two Title