F-Tile CPRI PHY Intel® FPGA IP User Guide

ID 683284
Date 10/04/2021
Public

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5.3. TX MII Interface (64b/66b)

Table 17.  TX MII Interface
Port Name Width (Bits) Domain Description
i_tx_mii_d[63:0] 64 o_tx_clkout2

TX MII data. Data must be in MII encoding. i_tx_mii_d[7:0] holds the first byte the IP core transmits on the CPRI link. i_tx_mii_d[0] holds the first bit the IP core transmits on the CPRI link.

i_tx_mii_c[7:0] 8 o_tx_clkout2 TX MII control bits. Each bit corresponds to a byte of the TX MII data signal. For example, i_tx_mii_c[0] corresponds to i_tx_mii_d[7:0], i_tx_mii_c[1] corresponds to i_tx_mii_d[15:8], and so on.

If the value of a bit is 1, the corresponding data byte is a control byte. If the value of a bit is 0, the corresponding data byte is data.

The Start of Packet byte (0xFB) and End of Packet byte (0xFD) are control bytes.

Figure 8. Transmitting Data Using TX MII Interface

The figure above shows how to write packets directly to the TX MII interface.

  • The packets are written using MII.
    • Each byte in i_tx_mii_d has a corresponding bit in i_tx_mii_c that indicates whether the byte is a control byte or a data byte; for example, i_tx_mii_c[1] is the control bit for i_tx_mii_d[15:8].
  • The byte order for the TX MII interface flows from right to left; the first byte to be transmitted from the interface is i_tx_mii_d[7:0].
  • The first bit to be transmitted from the interface is i_tx_mii_d[0].