F-Tile CPRI PHY Intel® FPGA IP User Guide

ID 683284
Date 10/04/2021
Public

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5.1.1. Required Clock Frequencies

Table 15.  Required Clock Frequencies
Port Name Frequency (MHz) Notes
i_reconfig_clk 100 Used for CSR access on all the AVMM interfaces.
o_tx_clkout 402.83203125

415.0390625

451.5625

System clock divided by 2.
o_tx_clkout2 368.64 CPRI PHY system clock times (64/66) for 24G channels.
184.32 CPRI PHY system clock times (64/66) for 12G channels.
153.6 CPRI PHY system clock times (64/66) for 10G channels.
491.52 CPRI PHY system clock for 9.8G channels.
245.76 CPRI PHY system clock for 4.9G channels.
122.88 CPRI PHY system clock for 2.4G channels.
o_rx_clkout 402.83203125

415.0390625

451.5625

System clock divided by 2
o_rx_clkout2 368.64 Derived from recovered clock for 24G channels.
184.32 Derived from recovered clock for 12G channels.
153.6 Derived from recovered clock for 10G channels.
491.52 CPRI PHY system clock for 9.8G channels.
245.76 Derived from recovered clock for 4.9G channels.
122.88 CPRI PHY system clock for 2.4G channels.
i_sampling_clk 250 Sampling clock for deterministic logic from external source.