F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

ID 683281
Date 6/21/2022

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4. Document Revision History for F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.06.21 22.2 3.3.0
  • Added the hardware design example support for:
    • Intel® Agilex™ I-Series FPGA Development Kit
    • Intel® Agilex™ I-Series Transceiver-SoC Development Kit
  • Updated the Hardware and Software Requirements section.
2022.03.28 22.1 3.2.0
  • Removed support for ModelSim* SE simulator.
  • Updated the SIM_MODE parameter description in section: Packet Client.
2021.12.13 21.4 3.1.0
  • Added support for Cadence Xcelium* simulator.
  • Added support for Transceiver Toolkit.
  • Added new section: Design Example Components.
2021.10.04 21.3 3.0.0
  • Added support for new simulators in section: Hardware and Software Requirements.
  • Updated steps in section: Simulating the Design Example Testbench.
  • Updated the following sections with new line rate information:
    • Design Example Description
    • Simulation Design Example
    • Interface Signals
  • Updated the address in section: Design Example Registers.
2021.06.21 21.2 2.0.0 Initial release.