F-Tile CPRI PHY Intel® FPGA IP Design Example User Guide

ID 683281
Date 6/21/2022

A newer version of this document is available. Customers should click here to go to the newest version.

2.2.5. JTAG Host

The JTAG to Avalon Host Bridge Intel FPGA IP sends and receives commands from system console to example design’s Avalon® memory-mapped interface (host of Avalon memory-mapped decoder) via JTAG. In simulation, this block is bypassed, and replaced with a Verilog force statement. The Avalon® memory-mapped interface read and write task simulates the system console operation. For more information, refer to SPI Agent/JTAG to Avalon Host Bridge Cores.