E-Tile JESD204C Intel® FPGA IP Release Notes

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ID 683266
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. E-Tile JESD204C Intel® FPGA IP Release Notes 2. E-Tile JESD204C Intel® FPGA IP User Guide Archives 3. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives 4. E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
1. E-Tile JESD204C Intel® FPGA IP Release Notes x
1.1. JESD204C Intel® FPGA IP v3.1.1 1.2. JESD204C Intel® FPGA IP v2.0.0 1.3. JESD204C Intel® FPGA IP v1.1.0 1.4. JESD204C Intel® FPGA IP v1.0.0 1.5. JESD204C Intel® FPGA IP v1.0.0
1. E-Tile JESD204C Intel® FPGA IP Release Notes
2. E-Tile JESD204C Intel® FPGA IP User Guide Archives
3. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives
4. E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives

1.4. JESD204C Intel® FPGA IP v1.0.0

Table 5.  v1.0.0 2019.09.30
Intel® Quartus® Prime Version Description Impact
19.3 Added advance support for Intel Agilex® 7 E-tile devices. The Intel Agilex® 7 E-tile devices are now supported in the 19.3 version of the Intel® Quartus® Prime Pro Edition software. Upgrade your IP to use the new features.

Added the following presets for Intel Agilex® 7 devices:

  • LMF = 2812, 24.333 Gbps
  • LMF = 484, 16.222 Gbps
You can simulate these presets through the Example Design tab in the JESD204C IP parameter editor.
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