E-Tile JESD204C IP Release Notes

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ID 683266
Date 9/04/2025
Public

1.4. JESD204C Intel® FPGA IP v1.1.0

Table 4.  v1.1.0 2020.04.13
Quartus® Prime Version Description Impact
20.1 Updated the supported data rates for FPGA fabric speed grades for Stratix® 10 and Agilex™ 7 E-tile devices. –
Added a new GUI parameter, Multilink mode. When enabled, the multilink mode implements synchronization between multiple JESD204C RX IP instances.

These changes are optional. If you do not upgrade your IP core, it does not have these new features.
Added the following signals for multilink mode:
  • j204c_rx_dev_emblock_align
  • j204c_rx_alldev_emblock_align
Table 5.  v1.1.0 2019.12.16
Quartus® Prime Version Description Impact
19.4 Updated the supported maximum data rate to 28.9 Gbps for Stratix® 10 and Agilex™ 7 E-tile devices. –
Optimized area utilization for JESD204C RX IP.
Enabled hardware design example for Agilex™ 7 devices.

You can generate the design example using the Agilex™ 7 Signal Integrity development kit.
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