E-Tile JESD204C Intel® FPGA IP Release Notes

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ID 683266
Date 10/02/2023
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Document Table of Contents x
1. E-Tile JESD204C Intel® FPGA IP Release Notes 2. E-Tile JESD204C Intel® FPGA IP User Guide Archives 3. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives 4. E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
1. E-Tile JESD204C Intel® FPGA IP Release Notes x
1.1. JESD204C Intel® FPGA IP v3.1.1 1.2. JESD204C Intel® FPGA IP v2.0.0 1.3. JESD204C Intel® FPGA IP v1.1.0 1.4. JESD204C Intel® FPGA IP v1.0.0 1.5. JESD204C Intel® FPGA IP v1.0.0
1. E-Tile JESD204C Intel® FPGA IP Release Notes
2. E-Tile JESD204C Intel® FPGA IP User Guide Archives
3. E-Tile JESD204C Intel Agilex® 7 FPGA IP Design Example User Guide Archives
4. E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives

1.3. JESD204C Intel® FPGA IP v1.1.0

Table 3.  v1.1.0 2020.04.13
Intel® Quartus® Prime Version Description Impact
20.1 Updated the supported data rates for FPGA fabric speed grades for Intel® Stratix® 10 and Intel Agilex® 7 E-tile devices. –
Added a new GUI parameter, Multilink mode. When enabled, the multilink mode implements synchronization between multiple JESD204C RX IP instances.

These changes are optional. If you do not upgrade your IP core, it does not have these new features.

Added the following signals for multilink mode:
  • j204c_rx_dev_emblock_align
  • j204c_rx_alldev_emblock_align
Table 4.  v1.1.0 2019.12.16
Intel® Quartus® Prime Version Description Impact
19.4 Updated the supported maximum data rate to 28.9 Gbps for Intel® Stratix® 10 and Intel Agilex® 7 E-tile devices. –
Optimized area utilization for JESD204C RX IP.
Enabled hardware design example for Intel Agilex® 7 devices.

You can generate the design example using the Intel Agilex® 7 Signal Integrity development kit.

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