Intel® High Level Synthesis Compiler Standard Edition: Best Practices Guide

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ID 683259
Date 12/18/2019
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Document Table of Contents
Document Table of Contents x
1. Intel® HLS Compiler Standard Edition Best Practices Guide 2. Best Practices for Coding and Compiling Your Component 3. Interface Best Practices 4. Loop Best Practices 5. Memory Architecture Best Practices 6. Datatype Best Practices 7. Advanced Troubleshooting A. Intel® HLS Compiler Standard Edition Best Practices Guide Archives B. Document Revision History for Intel® HLS Compiler Standard Edition Best Practices Guide
3. Interface Best Practices x
3.1. Choose the Right Interface for Your Component 3.2. Avoid Pointer Aliasing
3.1. Choose the Right Interface for Your Component x
3.1.1. Pointer Interfaces 3.1.2. Avalon® Memory Mapped Master Interfaces 3.1.3. Avalon® Memory Mapped Slave Interfaces 3.1.4. Avalon® Streaming Interfaces 3.1.5. Pass-by-Value Interface
4. Loop Best Practices x
4.1. Reuse Hardware By Calling It In a Loop 4.2. Parallelize Loops 4.3. Construct Well-Formed Loops 4.4. Minimize Loop-Carried Dependencies 4.5. Avoid Complex Loop-Exit Conditions 4.6. Convert Nested Loops into a Single Loop 4.7. Declare Variables in the Deepest Scope Possible
4.2. Parallelize Loops x
4.2.1. Pipeline Loops 4.2.2. Unroll Loops 4.2.3. Example: Loop Pipelining and Unrolling
5. Memory Architecture Best Practices x
5.1. Example: Overriding a Coalesced Memory Architecture 5.2. Example: Overriding a Banked Memory Architecture 5.3. Merge Memories to Reduce Area 5.4. Example: Specifying Bank-Selection Bits for Local Memory Addresses
5.3. Merge Memories to Reduce Area x
5.3.1. Example: Merging Memories Depth-Wise 5.3.2. Example: Merging Memories Width-Wise
6. Datatype Best Practices x
6.1. Avoid Implicit Data Type Conversions 6.2. Avoid Negative Bit Shifts When Using the ac_int Datatype
7. Advanced Troubleshooting x
7.1. Component Fails Only In Cosimulation 7.2. Component Gets Bad Quality of Results
1. Intel® HLS Compiler Standard Edition Best Practices Guide
2. Best Practices for Coding and Compiling Your Component
3. Interface Best Practices
4. Loop Best Practices
5. Memory Architecture Best Practices
6. Datatype Best Practices
7. Advanced Troubleshooting
A. Intel® HLS Compiler Standard Edition Best Practices Guide Archives
B. Document Revision History for Intel® HLS Compiler Standard Edition Best Practices Guide

3.1.3. Avalon® Memory Mapped Slave Interfaces

Depending on your component, you can sometimes optimize the memory structure of your component by using Avalon® Memory Mapped (MM) slave interfaces.

When you allocate a slave memory, you must define its size. Defining the size puts a limit on how large a value of N that the component can process. In this example, the RAM size is 1024 words. This RAM size means that N can have a maximal size of 1024 words.

The vector addition component example can be coded with an Avalon® MM slave interface as follows: 
component void vector_add(
     hls_avalon_slave_memory_argument(1024*sizeof(int)) int* a,
     hls_avalon_slave_memory_argument(1024*sizeof(int)) int* b,
     hls_avalon_slave_memory_argument(1024*sizeof(int)) int* c,
     int N) {
  #pragma unroll 8
  for (int i = 0; i < N; ++i) {
    c[i] = a[i] + b[i];
  }
}
The following diagram shows the Component Viewer report generated when you compile this example.
Figure 3. Component View of vector_add Component with Avalon® MM Slave Interface


Compiling this component with an Intel® Quartus® Prime compilation flow targeting an Intel® Arria® 10 device results in the following QoR metrics:
Table 4.  QoR Metrics Comparison for Avalon® MM Slave Interface1
QoR Metric Pointer Avalon® MM Master Avalon® MM Slave
ALMs 15593.5 643 490.5
DSPs 0 0 0
RAMs 30 0 48
fMAX (MHz)2 298.6 472.37 498.26
Latency (cycles) 24071 142 139
Initiation Interval (II) (cycles) ~508 1 1
1The compilation flow used to calculate the QoR metrics used Intel® Quartus® Prime Pro Edition Version 17.1.
2The fMAX measurement was calculated from a single seed.
The QoR metrics show by changing the ownership of the memory from the system to the component, the number of ALMs used by the component are reduced, as is the component latency. The fMAX of the component is increased as well. The number of RAM blocks used by the component is greater because the memory is implemented in the component and not the system. The total system RAM usage (not shown) should not increase because RAM usage shifted from the system to the FPGA RAM blocks.
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