Intel® High Level Synthesis Compiler Standard Edition: Best Practices Guide

ID 683259
Date 12/18/2019
Public
Document Table of Contents
Give Feedback

5. Memory Architecture Best Practices

The Intel® High Level Synthesis Compiler infers efficient memory architectures (like memory width, number of banks and ports) in a component by adapting the architecture to the memory access patterns of your component. Review the memory architecture best practices to learn how you can get the best memory architecture for your component from the compiler.

In most cases, you can optimize the memory architecture by modifying the access pattern. However, the Intel® HLS Compiler Standard Edition gives you some control over the memory architecture.

Tutorials Demonstrating Memory Architecture Best Practices

The Intel® HLS Compiler comes with a number of tutorials that give you working examples to review and run so that you can see good coding practices as well as demonstrating important concepts.

Review the following tutorials to learn about memory architecture best practices that might apply to your design:
Table 7.  Tutorials Provided with Intel® HLS Compiler Standard Edition
Tutorial Description
You can find these tutorials in the following location on your Intel® Quartus® Prime system:
<quartus_installdir>/hls/examples/tutorials/
component_memories/bank_bits Demonstrates how to control component internal memory architecture for parallel memory access by enforcing which address bits are used for banking.
component_memories/depth_wise_merge Demonstrates how to improve resource utilization by implementing two logical memories as a single physical memory with a depth equal to the sum of the depths of the two original memories.
component_memories/width_wise_merge Demonstrates how to improve resource utilization by implementing two logical memories as a single physical memory with a width equal to the sum of the widths of the two original memories.