RapidIO Intel FPGA IP Core Release Notes

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ID 683256
Date 9/28/2020
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1.4. RapidIO IP Core v15.0

Table 4.  Version 15.0 May 2015
Description Impact Notes
The IP core loses lane synchronization when a lane receives three errored characters. Previously the IP core lost lane synchronization after receiving two errored characters on a lane. Lane synchronization is slightly more robust.  
Table 5.  RapidIO IP Core Signal ChangesSignals added or modified in version 15.0.
Old Signal Name New Signal Name Notes
— no_sync_indicator When this new output signal is low, it indicates at least one lane is not synchronized.
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