RapidIO Intel FPGA IP Core Release Notes

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Date 9/28/2020
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Product Discontinuance Notification 1. RapidIO Intel FPGA IP Core Release Notes 2. RapidIO Intel FPGA IP User Guide Archives
1. RapidIO Intel FPGA IP Core Release Notes x
1.1. RapidIO Intel FPGA IP v19.2.0 1.2. RapidIO Intel FPGA IP Core v18.0 1.3. RapidIO IP Core v15.1 1.4. RapidIO IP Core v15.0 1.5. RapidIO IP Core v14.1 1.6. RapidIO IP Core v14.0 Arria 10 Edition 1.7. RapidIO IP Core v14.0 1.8. RapidIO IP Core v13.1 1.9. RapidIO IP Core v13.0
Product Discontinuance Notification
1. RapidIO Intel FPGA IP Core Release Notes
2. RapidIO Intel FPGA IP User Guide Archives

1.6. RapidIO IP Core v14.0 Arria 10 Edition

Table 7.  Version 14.0 Arria 10 Edition August 2014
Description Impact Notes
Verified in the Quartus II software v14.0 Arria 10 Edition. (Added support for Arria 10 devices).

RapidIO IP core variations that target an Arria 10 device have the following differences from the variations that target earlier device families.

Upgrading your existing IP core from a previous release of the Quartus II software requires migrating it to the Arria 10 device family. To migrate your IP core to the Arria 10 device family, you must regenerate the IP core manually in the Quartus II v14.0 Arria 10 Edition software and reconnect it in your design.
Arria 10 variations require that you instantiate and connect a TX transceiver PLL IP core and a reset controller in your design. Upgrading your existing IP core from a previous release of the Quartus II software requires migrating it to the Arria 10 device family. To migrate your IP core to the Arria 10 device family, you must regenerate the IP core manually in the Quartus II v14.0 Arria 10 Edition software and reconnect it in your design. The new interface signals are listed in the RapidIO IP Core Signal Changes table.
Arria 10 variations do not require that you instantiate and connect a dynamic reconfiguration controller. Instead, if you turn on the new parameter Enable transceiver dynamic reconfiguration, these variations have an internal reconfiguration controller that the user accesses through an Avalon-MM interface. Upgrading your existing IP core from a previous release of the Quartus II software requires migrating it to the Arria 10 device family. To migrate your IP core to the Arria 10 device family, you must regenerate the IP core manually in the Quartus II v14.0 Arria 10 Edition software and reconnect it in your design. The new interface signals are listed in the RapidIO IP Core Signal Changes table.
If a RapidIO IP core that targets an Arria 10 device includes an I/O Logical layer Avalon-MM slave interface or an I/O Logical layer Avalon-MM master interface, the following conditions apply:
  • The IP core must include both an I/O Logical layer slave interface and an I/O Logical layer master interface. It cannot include one but not the other.
  • The I/O Logical layer slave module preserves transaction ordering between read and write operations.
  • The number of RX address translation windows is 16.
  • The number of TX address translation windows is 16.
Unsupported parameters and parameter values are not available in the parameter editor or cause error messages that block IP core generation. If your IP core is already in this subset of variations, you can recreate the precise variation. However, you must still regenerate the IP core manually and reconnect it in your design, because of other changes.
If a RapidIO IP core that targets an Arria 10 device includes an I/O Maintenance Logical layer module, the following conditions apply:
  • The module has both master and slave ports.
  • The number of Maintenance transmit address translation windows is 16.
  • The module supports both reception and transmission of port-write requests, or supports neither.
Unsupported parameters and parameter values are not available in the parameter editor or cause error messages that block IP core generation. If your IP core is already in this subset of variations, you can recreate the precise variation. However, you must still regenerate the IP core manually and reconnect it in your design, because of other changes.
A RapidIO IP core that targets an Arria 10 device supports both outbound and inbound DOORBELL messages, or it supports neither. Unsupported parameters and parameter values are not available in the parameter editor or cause error messages that block IP core generation. If your IP core is already in this subset of variations, you can recreate the precise variation. However, you must still regenerate the IP core manually and reconnect it in your design, because of other changes.
If a RapidIO IP core that targets an Arria 10 device supports DOORBELL messages, it preserves transaction order between DOORBELL messages and I/O write request transactions. Unsupported parameters and parameter values are not available in the parameter editor or cause error messages that block IP core generation. If your IP core is already in this subset of variations, you can recreate the precise variation. However, you must still regenerate the IP core manually and reconnect it in your design, because of other changes.
A RapidIO IP core that targets an Arria 10 device automatically synchronizes transmitted ackIDs. Unsupported parameters and parameter values are not available in the parameter editor or cause error messages that block IP core generation. If your IP core is already in this subset of variations, you can recreate the precise variation. However, you must still regenerate the IP core manually and reconnect it in your design, because of other changes.
In a RapidIO IP core that targets an Arria 10 device, the number of link-request attempts before declaring a fatal error is tied to 7. Unsupported parameters and parameter values are not available in the parameter editor or cause error messages that block IP core generation. If your IP core is already in this subset of variations, you can recreate the precise variation. However, you must still regenerate the IP core manually and reconnect it in your design, because of other changes.
In a RapidIO IP core that targets an Arria 10 device, the Physical layer receive and transmit buffers are 32 Kbytes each. Unsupported parameters and parameter values are not available in the parameter editor or cause error messages that block IP core generation. If your IP core is already in this subset of variations, you can recreate the precise variation. However, you must still regenerate the IP core manually and reconnect it in your design, because of other changes.
In the parameter editor for RapidIO IP core variations that target an Arria 10 device, the Disable Destination ID checking by default parameter is not available. Arria 10 variations do not check destination IDs, by default. However, support for controlling this feature through the IP core registers is available in all RapidIO IP core variations, as it was in the previous release. Unsupported parameters and parameter values are not available in the parameter editor or cause error messages that block IP core generation. If your IP core is already in this subset of variations, you can recreate the precise variation. However, you must still regenerate the IP core manually and reconnect it in your design, because of other changes.
Table 8.  RapidIO IP Core Signal ChangesSignals added or modified in version 14.0 Arria 10 Edition.
Old Signal Name New Signal Name Notes
— tx_bonded_clocks_ch<n>[5:0] New interface to external TX PLL. Relevant for Arria 10 variations only.

Individual transceiver channel clock signals. One signal (_ch<n>) for each RapidIO lane <n>.

— reconfig_clk_ch<n> New Arria 10 transceiver reconfiguration interface. This interface is available if you turn on Enable transceiver dynamic reconfiguration in the RapidIO parameter editor. Relevant for Arria 10 variations only.

One signal (_ch<n>) for each RapidIO lane <n>.

— reconfig_reset_ch<n>
— reconfig_read_ch<n>
— reconfig_write_ch<n>
— reconfig_address_ch<n>[9:0]
— reconfig_readdata_ch<n>[31:0]
— reconfig_waitrequest_ch<n>
— reconfig_writedata_ch<n>[31:0]
— tx_analogreset[N-1:0] New interface to external reset controller. Relevant for Arria 10 variations only.

N is the number of RapidIO lanes.

— rx_analogreset[N-1:0]
— tx_digitalreset[N-1:0]
— rx_digitalreset[N-1:0]
reconfig_togxb Not present in Arria 10 variations. Transceiver reconfiguration interface for Arria V, Cyclone V, and Stratix V variations. This interface is present only in Arria V, Cyclone V, and Stratix V variations (as supported in past and future versions of the Quartus II software). These signals are not present in Arria 10 variations.
reconfig_fromgxb Not present in Arria 10 variations.
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