Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 11/26/2024
Public
Document Table of Contents

2.4.2.2. Input Constraints (set_input_delay)

Input constraints specify delays for all external signals feeding the FPGA. Specify input requirements for all input ports in your design.
set_input_delay -clock { clock } -clock_fall -fall -max 20 foo

Use the Set Input Delay (set_input_delay) constraint to specify external input delay requirements. Specify the Clock name (-clock) to reference the virtual or actual clock. You can specify a clock to allow the Timing Analyzer to correctly derive clock uncertainties for interclock and intraclock transfers. The clock defines the launching clock for the input port. The Timing Analyzer automatically determines the latching clock inside the device that captures the input data, because all clocks in the device are defined.

Figure 94. Input Delay Diagram
Figure 95. Input Delay Calculation
Note: Beginning in Quartus® Prime Pro Edition software version 24.3, support for the blackbox argument is removed. You could previously use the blackbox argument to perform delay budgeting on I/Os at the boundary of a design partition. Refer to Deprecation of the blackbox Argument.

You can use the Check Timing (check_timing) command to report problems with a variety of timing constraints, such as the number of input ports that are not clocks that have no input delay constraint.