O-RAN Intel® FPGA IP User Guide

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ID 683238
Date 8/15/2023
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Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP 2. Getting Started with the O-RAN Intel® FPGA IP 3. O-RAN IP Functional Description 4. O-RAN IP Registers 5. O-RAN Intel FPGA IP User Guide Archive 6. Document Revision History for the O-RAN Intel® FPGA IP User Guide
1. About the O-RAN Intel® FPGA IP x
1.1. O-RAN Intel® FPGA IP Features 1.2. O-RAN Intel® FPGA IP Device Family Support 1.3. Release Information for the O-RAN Intel® FPGA IP 1.4. O-RAN Intel® FPGA IP Performance and Resource Utilization
2. Getting Started with the O-RAN Intel® FPGA IP x
2.1. Obtaining, Installing, and Licensing the O-RAN IP 2.2. Parameterizing the O-RAN IP 2.3. Generated IP File Structure
2.2. Parameterizing the O-RAN IP x
2.2.1. O-RAN IP Parameters
3. O-RAN IP Functional Description x
3.1. O-RAN IP Signals 3.2. O-RAN Intel® FPGA IP Error Handling 3.3. O-RAN Reset Transactions 3.4. O-RAN IP Streaming Mode 3.5. O-RAN IP Performance Counters 3.6. O-RAN IP Transmission and Reception Window Threshold 3.7. O-RAN IP Fragmentation
3.6. O-RAN IP Transmission and Reception Window Threshold x
3.6.1. O-RAN IP Examples for Transmission and Reception Window Thresholds
1. About the O-RAN Intel® FPGA IP
2. Getting Started with the O-RAN Intel® FPGA IP
3. O-RAN IP Functional Description
4. O-RAN IP Registers
5. O-RAN Intel FPGA IP User Guide Archive
6. Document Revision History for the O-RAN Intel® FPGA IP User Guide

3.1. O-RAN IP Signals

Connect and control the IP.
Table 7.  Clock Signals

The IP operates at 390.625 MHz clock frequency asynchronously with the Ethernet MAC. The IP uses the same synchronous clock as the eCPRI IP, which runs at 390.625 MHz.

Signal Name Direction Description
clk_tx Input Clock for the transmitter logic. The frequency of this clock is 390.625 MHz for 25 Gbps ( Intel® Stratix® 10 devices only) and 156.25 MHz for 10 Gbps. All transmitter interface signals are synchronous to clk_tx.
clk_rx Input Clock for the receiver logic. The frequency of this clock is 390.625 MHz for 10 or 25 Gbps ( Intel® Stratix® 10 devices only) and 156.25 MHz for 10 Gbps. All receiver interface signals are synchronous to clk_rx.
clk_csr Input Clock for the control and status register interface. The frequency of this clock is 100 MHz.
Table 8.  Reset Signals
Signal Name Direction Description
rst_tx_n Input Active low reset for transmitter interface synchronous to clk_tx.
rst_rx_n Input Active-low reset for receiver interface synchronous to clk_rx.
rst_csr_n Input Active-low reset for CSR interface synchronous to clk_csr.
tx_lanes_stable Input Indicates clk_tx clock signal is stable and transmitter path is ready to come out from reset.
rx_pcs_ready Input Indicates clk_rx clock signal is stable and receiver path is ready to come out from reset.
Table 9.  Interrupt Signals
Signal Bitwidth Direction Description
Irq 1 Output

Error interrupt signal. Indicates errors in the O-RAN IP. Software can poll Error Message register to determine error info.

The signal is synchronous to clk_csr.

Table 10.  Transmitter and Receiver TOD
Signal Bitwidth Direction Description
tx_time_of_day_96b_data 96 Input Current V2-format (96-bit) TOD in clk_txmac clock domain.
rx_time_of_day_96b_data 96 Input Current V2-format (96-bit) TOD in clk_rxmac clock domain.
Table 11.  CSR Signals
Signal Bitwidth Direction Description
csr_address 16 Input Config register address
csr_write 1 Input Config register write enable.
csr_writedata 32 Input Config register write data.
csr_readdata 32 Output Config register read data.
csr_read 1 Input Config register read enable.
csr_readdatavalid 1 Output Config register read data valid.
csr_waitrequest 1 Output Config register wait request.

Transport Interface

Table 12.  Transmitter SignalsAll transmitter interface signals are synchronous to clk_tx.
Signal Bitwidth Direction Description
avst_source_valid 1 Output When asserted, indicates valid data is available on avst_source_data.
avst_source_data 64 Output PRB fields including udCompParam, iSample and qSample. Next section PRB fields are concatenated to the previous section PRB field.
avst_source_startofpacket 1 Output Indicates first byte of a frame.
avst_source_endofpacket 1 Output Indicates last byte of a frame.
avst_source_ready 1 Input When asserted, indicates the transport layer is ready to accept data. readyLatency = 3 for this interface.
avst_source_empty 3 Output Specifies the number of empty bytes on avst_source_data when avst_source_endofpacket is asserted.
tx_transport_c_u 1 Output

Indicates if packets transmitted to transport layer is C-plane or U-plane packet:

0 = User IQ data

1 = Control message.
source_pc_id 16 Output Pcid for eCPRI transport and RoEflowId for RoE transport.
source_rtc_id 16 Output Rtcid for eCPRI transport and RoEflowId for RoE transport.
source_seq_id 16 Output Indicates the sequence ID of the packet. The eCPRI transport header uses this field.
source_pkt_size 16 Output O-RAN packet size in bytes for the data packet from client logic to the IP. This signal is available only when you select 9000 for the Maximum Ethernet frame size. You must connect this signal to the sink_pkt_size signal of the eCPRI Intel FPGA IP when you turn on Streaming in the eCPRI IP.
Figure 10. Transport Transmitter Interface Timing DiagramTransport interface signals transmit O-RAN packet.
Table 13.  Receiver SignalsAll receiver interface signals are synchronous to clk_rx.
Signal Bitwidth Direction Description
avst_sink_valid 1 Input When asserted, indicates valid data is available on avst_sink_data.
avst_sink_data 64 Input PRB fields including udCompParam, iSample and qSample. Next section PRB fields concatenate to previous section PRB field.
avst_sink_startofpacket 1 Input Indicates first byte of a frame.
avst_sink_endofpacket 1 Input Indicates last byte of a frame.
avst_sink_empty 3 Input Specifies the number of empty bytes on avst_sink_data when avst_sink_endofpacket is asserted.
avst_sink_error 1 Input When asserted in the same cycle as avst_sink_endofpacket, indicates the current packet is as an error packet.
rx_transport_c_u 1 Input

Indicates if packets received from transport layer is C-plane or U-plane packet

0 = User IQ data

1 = Control message.
sink_pc_id 16 Input Pcid for eCPRI transport and RoEflowId for RoE transport.
sink_rtc_id 16 Input Rtcid for eCPRI transport and RoEflowId for RoE transport.
sink_seq_id 16 Input Indicates the sequence ID of the packet. The IP extracts this field from eCPRI transport header.

Application Interface Transmitter Signals

Table 14.  Control PlaneAll transmitter interface signals are synchronous to clk_tx.
Signal Bitwidth Direction Description
avst_sink_c_valid 1 Input When asserted, indicates valid section is available in this interface. When in streaming mode, ensure no valid signal deassertions are between the SOP and the EOP, except when ready signal is deasserted.
avst_sink_c_startofpacket 1 Input Indicates the first section of a packet.
avst_sink_c_endofpacket 1 Input Indicates the last section of a packet.
avst_sink_c_ready 1 Output When asserted, indicates the O-RAN IP is ready to accept data from application interface. readyLatency = 0 for this interface.
tx_c_size 16 Input C-plane packet size in bytes for the data packet from client logic to the IP. This signal is available only when you select 9000 for the Maximum Ethernet frame size.
tx_c_rtc_id 16 Input Rtcid for eCPRI transport and RoEflowId for RoE transport.
tx_c_seq_id 16 Input SeqID of the packet appended to eCPRI transport header.
tx_c_dataDirection 1 Input Drives common header IEs to the same value between avst_sink_c_startofpacket and avst_sink_c_endofpacket.
tx_c_filterIndex 4 Input
tx_c_frameId 8 Input
tx_c_subframeId 4 Input
tx_c_slotID 6 Input
tx_c_symbolid 6 Input
tx_sectionType 8 Input Drives section header IEs to the same value between avst_sink_c_startofpacket and avst_sink_c_endofpacket.
tx_timeOffset 16 Input
tx_frameStructure 8 Input
tx_cpLength 16 Input
tx_c_udCompHdr 8 Input
tx_c_sectionId 12 Input Repeated section IEs synchronous with avst_sink_c_valid. For every cycle with avst_sink_c_valid = 1, the IP accepts new section IEs for mapping to the same packet between avst_sink_c_startofpacket and avst_sink_c_endofpacket.
tx_c_rb 1 Input
tx_c_startPrb 10 Input
tx_c_numPrb 8 Input
tx_reMask 12 Input
tx_ef 1 Input
tx_beamid 15 Input
tx_numSymbol 4 Input
tx_frequencyOffset 24 Input
tx_ext_sectionType 8 Input Indicates which section type is associate for this section extension.
avst_sink_c_ext_valid 1 Input When asserted, indicates valid section extension is available in this interface.
avst_sink_c_ext_startofpacket 1 Input Indicates the first section extension of a packet.
avst_sink_c_ext_endofpacket 1 Input Indicates the last section extension of a packet.
avst_sink_c_ext_data 64 Input Section extension data from application layer in network byte order.
avst_sink_c_ext_empty 3 Input Specifies the number of empty bytes on avst_sink_c_ext_data when avst_sink_c_ext_endofpacket is asserted.
avst_sink_c_ext_ready 1 Output When asserted, indicates the O-RAN IP is ready to accept data from application interface. readyLatency = 0 for this interface.
Figure 11. Application Transmitter Interface Control Plane Timing Diagram Avalon streaming sink, common header, and section header IEs are the same for entire packet. Only repeated section IEs vary for every avst_sink_c_valid cycle.
Table 15.  User Plane SignalsAll transmitter interface signals are synchronous to clk_tx.
Signal Bitwidth Direction Description
avst_sink_u_valid 1 Input When asserted, indicates valid physical resource block (PRB) fields are available in this interface. When in streaming mode, ensure no valid signal deassertions are between the SOP and the EOP, except when ready signal is deasserted.
avst_sink_u_data 64/128 Input PRB fields including udCompParam, iSample and qSample. The IP concatenates next section PRB fields to previous section PRB field. Data to transport layer in network byte order. Data width is 128 when EN_COMPANSION = 1.
avst_sink_u_startofpacket 1 Input Indicates the first PRB byte of a packet.
avst_sink_u_endofpacket 1 Input Indicates the last PRB byte of a packet.
avst_sink_u_empty 3 Input Indicates the number of empty bytes during end-of-packet. This signal only exists when EN_COMPANSION = 0.
avst_sink_u_ready 1 Output When asserted, indicates the O-RAN IP is ready to accept data from the application interface. readyLatency = 0 for this interface.
tx_u_size 16 Input U-plane packet size in bytes for the data packet from client logic to the IP. This signal is available only when you select 9000 for the Maximum Ethernet frame size.

When you turn on U-Plane Fragmentation, the IP updates this field based on fragmented number of PRBs.

When you turn off U-Plane Fragmentation, logic must provide the correct value to the IP (compressed packet size in bytes if Enable companding is on).

tx_u_pc_id 16 Input Pcid for eCPRI transport and RoEflowId for RoE transport.
tx_u_seq_id 16 Input SeqID of the packet appended to the eCPRI transport header.
tx_u_dataDirection 1 Input Drives common header IEs to the same value between avst_sink_u_startofpacket and avst_sink_u_endofpacket.
tx_u_filterIndex 4 Input
tx_u_frameId 8 Input
tx_u_subframeId 4 Input
tx_u_slotID 6 Input
tx_u_symbolid 6 Input
tx_u_sectionId 12 Input Repeated section IEs synchronous with avst_sink_u_valid. On presenting new section PRB fields in avst_sink_u_data, present new section IEs in these ports.
tx_u_rb 1 Input
tx_u_startPrb 10 Input
tx_u_numPrb 8 Input
tx_u_udCompHdr 8 Input
Figure 12.  Application Interface Transmitter User Plane Timing Diagram

Application interface signals receive IEs with single PRB. The IP maintains the Avalon streaming sink, common header, and section header IEs the same for the entire packet

Application Interface Receiver Signals

Table 16.  Control Plane SignalsAll receiver interface signals are synchronous to clk_rx.
Signal Bitwidth Direction Description
avst_source_c_valid 1 Output When asserted, indicates valid section is available in this interface.
avst_source_c_startofpacket 1 Output Indicates the first section of a packet.
avst_source_c_endofpacket 1 Output Indicates the last section of a packet.
avst_source_c_error 1 Output Indicates the packets contains error.
rx_c_rtc_id 16 Output Rtcid for eCPRI transport and RoEflowId for RoE transport.
rx_c_seq_id 16 Output SeqID of the packet, which the IP extracts from eCPRI transport header
rx_c_dataDirection 1 Output Drives common header IEs to the same value between avst_source_c_startofpacket and avst_source_c_endofpacket.
rx_c_filterIndex 4 Output
rx_c_frameId 8 Output
rx_c_subframeId 4 Output
rx_c_slotID 6 Output
rx_c_symbolid 6 Output
rx_sectionType 8 Output Drives section header IEs to the same value between avst_source_c_startofpacket and avst_source_c_endofpacket.
rx_timeOffset 16 Output
rx_frameStructure 8 Output
rx_cpLength 16 Output
rx_c_udCompHdr 8 Output
rx_c_sectionId 12 Output Repeated section IEs synchronous with avst_source_c_valid. For every cycle with avst_source_c_valid = 1, new section IEs stream out from same packet between avst_source_c_startofpacket and avst_source_c_endofpacket.
rx_c_rb 1 Output
rx_c_startPrbc 10 Output
rx_c_numPrbc 8 Output
rx_reMask 12 Output
rx_ef 1 Output
rx_beamid 15 Output
rx_numSymbol 4 Output
rx_frequencyOffset 24 Output
avst_source_c_ext_valid 1 Output When asserted, indicates valid section extension is available in this interface.
avst_source_c_ext_startofpacket 1 Output Indicates the first section extension of a packet.
avst_source_c_ext_endofpacket 1 Output Indicates the last section extension of a packet.
avst_source_c_ext_error 1 Output Indicates the packets contain errors.
avst_source_c_ext_data 64 Output Section extension data to the application layer in network byte order.
avst_source_c_ext_empty 3 Output Specifies the number of empty bytes on avst_source_c_ext_data when avst_source_c_ext_endofpacket is asserted.
rx_ext_sectionType 8 Output Indicates which section type is associate for this section extension.
Figure 13.  Application Interface Receiver Control Plane Timing Diagram
Table 17.  User Plane SignalsAll receiver interface signals are synchronous to clk_rx.
Signal Bitwidth Direction Description
avst_source_u_valid 1 Output When asserted, indicates valid PRB fields are available in this interface.
avst_source_u_data 64/128 Output PRB fields including udCompParam, iSample and qSample. Next section PRB fields are concatenated to previous section PRB field. Data width is 128 when EN_COMPANSION = 1.
avst_source_u_startofpacket 1 Output Indicates the first PRB byte of a packet.
avst_source_u_endofpacket 1 Output Indicates the last PRB byte of a packet.
avst_source_u_empty 3 Output Indicates the number of empty bytes during end-of-packet. This signal only exists when EN_COMPANSION = 0.
avst_source_u_error 1 Output Indicates the packets contain errors.
rx_u_pc_id 16 Output Pcid for eCPRI transport and RoEflowId for RoE transport.
rx_u_seq_id 16 Output SeqID of the packet, which the IP extracts from eCPRI transport header.
rx_sec_hdr_valid 1 Output

Indicates the section data fields are valid. Drives constant 0 for C-plane packet.
rx_u_dataDirection 1 Output Common header IEs are valid when rx_sec_hdr_valid is asserted, synchronous with avst_source_u_startofpacket and avst_source_u_valid
rx_u_filterIndex 4 Output
rx_u_frameId 8 Output
rx_u_subframeId 4 Output
rx_u_slotID 6 Output
rx_u_symbolid 6 Output
rx_u_sectionId 12 Output Repeated section IEs are valid when rx_sec_hdr_valid is asserted, synchronous with avst_source_u_valid. On presenting new section PRB fields in avst_source_u_data, present new section IEs in these ports.
rx_u_rb 1 Output
rx_u_startPrb 10 Output
rx_u_numPrb 8 Output
rx_u_udCompHdr 8 Output
Figure 14.  Application Interface Receiver User Plane Timing DiagramThe application interface signals send to the user logic with a single PRB. The IP maintains the Avalon streaming sink, common header and section header IEs the same for the entire packet.
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