SDI II Intel® Arria 10 FPGA IP Design Example User Guide

ID 683209
Date 12/09/2022

2. SDI II Intel® FPGA IP Design Example Detailed Description

The SDI II Intel® FPGA IP core includes these design examples for Intel® Arria® 10 devices.
  • Parallel loopback with external VCXO
  • Parallel loopback without external VCXO
  • Serial loopback


  • For HD/3G-SDI single rate and triple rate designs, you can choose either CMU or fPLL as the TX PLL.
  • All designs use LED status for early debugging stage.
  • The simplex serial loopback designs include RX and TX options. To use RX or TX only components, remove the irrelevant blocks from the designs.
    User Requirement Preserve Remove
    RX Only RX Top
    • TX Top
    • Transceiver Arbiter
    TX Only TX Top
    • RX Top
    • Transceiver Arbiter
    Note: You can directly connect the Avalon-MM pins at the RX or TX Top as shown in the diagram below.
Figure 8. Components Required for Intel® Arria® 10 TX or RX Only Design

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