FIR II IP Intel® FPGA IP: User Guide

ID 683208
Date 5/10/2024
Document Table of Contents

1. About the FIR II IP Intel® FPGA IP

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 19.2.4
The IP provides a fully-integrated finite impulse response (FIR) filter function optimized for use with FPGA devices. The IP has an interactive parameter editor that allows you to easily create custom FIR filters. The parameter editor outputs IP functional simulation model files for use with Verilog HDL and VHDL simulators.

You can use the parameter editor to implement a variety of filter types, including single rate, decimation, interpolation, and fractional rate filters.

Many digital systems use signal filtering to remove unwanted noise, to provide spectral shaping, or to perform signal detection or analysis. FIR filters and infinite impulse response (IIR) filters provide these functions. Typical filter applications include signal preconditioning, band selection, and low-pass filtering.

Figure 1. Basic FIR Filter with Weighted Tapped Delay Line

To design a filter, identify coefficients that match the frequency response you require for your system. These coefficients determine the response of the filter. You can change which signal frequencies pass through the filter by changing the coefficient values in the parameter editor.