SoC FPGA Embedded Development Suite (EDS) Standard Version 20.1 Release Notes

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ID 683202
Date 6/12/2020
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SoC FPGA Embedded Development Suite (EDS) Standard Version 20.1 Release Notes
SoC FPGA Embedded Development Suite (EDS) Standard Version 20.1 Release Notes x
New Features and Enhancements Tool Versions Known Issues SoC FPGA Embedded Development Suite Archives Revision History for SoC FPGA Embedded Development Suite (EDS) Release Notes
SoC FPGA Embedded Development Suite (EDS) Standard Version 20.1 Release Notes

New Features and Enhancements

Table 1.  New Features and Enhancements for SoC EDS Standard Edition version 20.1
Area Description
Arm* Development Studio* for Intel® SoC FPGA Edition Arm* DS-5* for Intel® SoC FPGA Edition is not part of the SoC FPGA EDS package. Instead, it is replaced by Arm* DS* for Intel® SoC FPGA Edition which can be downloaded from the Download Center for FPGAs website.
Hardware Library (HWLib)
  • Added the ability to use:
    • Linaro* GCC compiler
    • Standard C library for embedded systems: newlib
  • Removed Mentor Graphics* CS3 dependency
  • Added hardware init source
Python and OpenJDK
  • All software examples have been updated to use the Linaro* toolchain by default
  • OpenJDK upgraded to match Intel® Quartus® Prime Standard Edition version 20.1
  • Host tools scripts upgraded to Python 3.8.1, including a rewrite for some of the secure boot tools
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