1. Stratix® 10 Clocking and PLL Overview
2. Stratix® 10 Clocking and PLL Architecture and Features
3. Stratix® 10 Clocking and PLL Design Considerations
4. Stratix® 10 Clocking and PLL Implementation Guides
5. Clock Control Intel® FPGA IP Core References
6. IOPLL Intel® FPGA IP Core References
7. IOPLL Reconfig Intel® FPGA IP Core References
8. Stratix® 10 Clocking and PLL User Guide Archives
9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Architecture
2.2.4. PLL Control Signals
2.2.5. Clock Feedback Modes
2.2.6. Clock Multiplication and Division
2.2.7. Programmable Phase Shift
2.2.8. Programmable Duty Cycle
2.2.9. PLL Cascading
2.2.10. Clock Switchover
2.2.11. PLL Reconfiguration and Dynamic Phase Shift
2.2.12. PLL Calibration
4.3.4.1. Design Example 1: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.2. Design Example 2: Advanced Mode Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.4. Design Example 4: Dynamic Phase Shift Using IOPLL Reconfig IP Core
2.2.12. PLL Calibration
I/O PLLs include both analog and digital blocks that require calibration to compensate for process, voltage, and temperature (PVT) variations. Stratix® 10 uses the I/O manager to perform calibration routines.
There are two main types of calibration.
- Power-up calibration—Initiates automatically at device power-up and runs during device configuration.
- User calibration—If you perform dynamic reconfiguration or change the reference clock frequency of the I/O PLL, you must perform user recalibration. You must enable the required calibration sequence.
To successfully complete the calibration process, OSC_CLK_1 clocks and all reference clocks driving the I/O PLLs must be stable and free running at the start of FPGA configuration. If clock switchover is enabled, both reference clocks must be present for calibration. During user mode, when the I/O PLL does not detect a reference clock during configuration, calibration attempts continue periodically. After calibration has completed, the I/O PLL is locked automatically.
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