Stratix® 10 Clocking and PLL User Guide

ID 683195
Date 4/01/2024
Document Table of Contents

2.2.5. Clock Feedback Modes

Clock feedback modes compensate for clock network delays to align the rising edge of the output clock with the rising edge of the PLL's reference clock. Select the appropriate type of compensation for the timing critical clock path in your design.

PLL compensation is not always needed. A PLL should be configured in direct (no compensation) mode unless a need for compensation is identified. Direct mode provides the best PLL jitter performance and avoids expending compensation clocking resources unnecessarily.

The default clock feedback mode is direct compensation mode.

fPLLs support only the direct compensation mode.

I/O PLLs support the following clock feedback modes:

  • Direct compensation
  • LVDS compensation
  • Source synchronous compensation
  • Normal compensation
  • Zero delay buffer (ZDB) compensation
  • External feedback (EFB) compensation

Normal and source synchronous compensation modes compensate for the insertion delay of a routed core clock. For Stratix® 10 devices, you can achieve core clock compensation by the following methods:

  • You can route a dedicated feedback clock from the M counter in the I/O PLL to emulate the insertion delay of the compensated C counter output clock network.
  • You can select Use Nondedicated Feedback Path from the IOPLL Intel® FPGA IP core which routes the compensated C counter output clock back to the I/O PLL.

Intel recommends the non-dedicated feedback mechanism because it utilizes the clock resources most efficiently. The default is dedicated feedback when you choose normal or source synchronous compensation mode in the IOPLL IP core.