1. Stratix® 10 Clocking and PLL Overview
2. Stratix® 10 Clocking and PLL Architecture and Features
3. Stratix® 10 Clocking and PLL Design Considerations
4. Stratix® 10 Clocking and PLL Implementation Guides
5. Clock Control Intel® FPGA IP Core References
6. IOPLL Intel® FPGA IP Core References
7. IOPLL Reconfig Intel® FPGA IP Core References
8. Stratix® 10 Clocking and PLL User Guide Archives
9. Document Revision History for the Stratix® 10 Clocking and PLL User Guide
2.2.1. PLL Features
2.2.2. PLL Usage
2.2.3. PLL Architecture
2.2.4. PLL Control Signals
2.2.5. Clock Feedback Modes
2.2.6. Clock Multiplication and Division
2.2.7. Programmable Phase Shift
2.2.8. Programmable Duty Cycle
2.2.9. PLL Cascading
2.2.10. Clock Switchover
2.2.11. PLL Reconfiguration and Dynamic Phase Shift
2.2.12. PLL Calibration
4.3.4.1. Design Example 1: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.2. Design Example 2: Advanced Mode Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.3. Design Example 3: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
4.3.4.4. Design Example 4: Dynamic Phase Shift Using IOPLL Reconfig IP Core
2.2.12.1. Power-Up Calibration
After device power-up, the I/O manager automatically initiates the calibration process. The process continues during device programming.
You must enable the permit_cal signal from the IOPLL IP core to delay the power-up calibration in I/O PLL if the reference clock is not stable before device configuration. Set permit_cal = 0 upon power up until the reference clock is stable and operating at the correct frequency. Then, set permit_cal = 1 to initiate the power-up calibration. You must ensure that the permit_cal signal remains high once asserted.
Figure 22. Example of Power-Up Calibration When PLL Reference Clock is Not Stable Upon Power UpThis is an example on how to set permit_cal = 0 when the PLL reference clock is not stable before device configuration. You can invert the I/O PLL reset signal and connect it to the permit_cal port as shown in this figure. Asserting the reset signal high delays power-up calibration. Deassert the reset signal once the clock driving the I/O PLL is stable to initiate the power-up calibration.