Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization
ID
683174
Date
5/28/2025
Public
1.3.2.1. Using Simulation Signal Activity Data in Power Analysis
1.3.2.2. Signal Activities from RTL (Functional) Simulation, Supplemented by Vectorless Estimation
1.3.2.3. Signal Activities from Vectorless Estimation and User-Supplied Input Pin Activities
1.3.2.4. Signal Activities from User Defaults Only
1.5.1. Complete Design Simulation Power Analysis Flow
1.5.2. Modular Design Simulation Power Analysis Flow
1.5.3. Multiple Simulation Power Analysis Flow
1.5.4. Overlapping Simulation Power Analysis Flow
1.5.5. Partial Design Simulation Power Analysis Flow
1.5.6. Vectorless Estimation Power Analysis Flow
2.4.1. Clock Power Management
2.4.2. Pipelining and Retiming
2.4.3. Architectural Optimization
2.4.4. I/O Power Guidelines
2.4.5. Dynamically Controlled On-Chip Terminations (OCT)
2.4.6. Memory Optimization (M20K/MLAB)
2.4.7. DDR Memory Controller Settings
2.4.8. DSP Implementation
2.4.9. Reducing High-Speed Tile (HST) Usage
2.4.10. Unused Transceiver Channels
2.4.11. Periphery Power reduction XCVR Settings
2.3.3. Area-Driven Synthesis
Using area optimization rather than timing or delay optimization during synthesis saves power because you use fewer logic blocks. Using less logic usually means less switching activity.
The Quartus® Prime software provides Speed, Balanced, or Area for the Optimization Technique option. You can also specify this logic option for specific modules in your design with the Assignment Editor in cases where you want to reduce area using the Area setting (potentially at the expense of register-to-register timing performance) while leaving the default Optimization Technique setting at Balanced (for the best trade-off between area and speed for certain device families). The Speed Optimization Technique can increase the resource usage of your design if the constraints are too aggressive and can also result in increased power consumption.
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